https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/ 2026-04-05T15:14:36+00:00 https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/ https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/_media/wiki:dokuwiki-128.png text/html 2007-12-17T18:54:11+00:00 roumani (roumani@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/whats_new?rev=1197917651&do=diff Announcements New announcements will be posted here in reverse chronological order. ---------- Mon Dec. 17, 07 * The overall grades are available on ePost. ---------- Mon Dec. 10, 07 * The results of LabTest #2 are available on ePost and so are the reappraisals of Test #2. text/html 2007-12-01T20:21:27+00:00 roumani (roumani@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/tests?rev=1196540487&do=diff Assessment As indicated in the Grades page, assessment in this course is based on performing eight pass/fail labs and taking four tests and an exam. The four tests are held during the term at the dates specified in the Calendar page. The exam is held during the final examination period at a date/place set by the Registrar Office. This page provides information about the tests and the exam in term of policies, scope, and outline. text/html 2007-11-24T21:21:24+00:00 roumani (roumani@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/caches?rev=1195939284&do=diff Caches Caching is a technique for improving the performance of any process if the process is likely to be executed more than once. It is used for example by browsers to speed up access to web pages when they are re-visited. It is also used by RAID controllers to speed up access to disk, by TLBs to speed up the virtual-to-physical address translation, and by CPUs to speed up DRAM access. This lecture explores the concepts that underlie caching. It covers single versus multi-word blocks, direct-m… text/html 2007-11-23T20:45:04+00:00 roumani (roumani@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/pipelines?rev=1195850704&do=diff Pipelining This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU not by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is also