https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/ 2026-04-06T21:35:28+00:00 https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/ https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/_media/wiki:dokuwiki-128.png text/html 2007-09-23T18:50:21+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/assembly_language?rev=1190573421&do=diff Assembly Language This lecture covers Program Execution (a closer look at DRAM, the CPU, and the fetch-execute cycle) and introduces assembly language. The SPIM simulator is used to demonstrate writing and running programs for the MIPS family of processors. text/html 2007-11-24T21:21:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/caches?rev=1195939284&do=diff Caches Caching is a technique for improving the performance of any process if the process is likely to be executed more than once. It is used for example by browsers to speed up access to web pages when they are re-visited. It is also used by RAID controllers to speed up access to disk, by TLBs to speed up the virtual-to-physical address translation, and by CPUs to speed up DRAM access. This lecture explores the concepts that underlie caching. It covers single versus multi-word blocks, direct-m… text/html 2007-11-23T15:42:29+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/calendar?rev=1195832549&do=diff Calendar NO. WEEK OF Lab Mon 6pm Lab Tue 7pm Lecture Thu 7pm 1 Sept. 3 Foundational Concepts 2 Sept. 10 DRep DRep 3 Sept. 17 DRep DRep Assembly Language 4 Sept. 24 Lab A Lab A Meet the Families 5 Oct. 1 Lab B Lab B text/html 2007-07-31T19:53:17+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/course_outline?rev=1185911597&do=diff Course Outline The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed: Week 1 Your notes here. Week 2 Midterm Drop Deadline Week 13 Final Exam text/html 2007-10-30T17:51:03+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/digital_logic?rev=1193766663&do=diff Digital Logic This lecture crosses the elusive software - hardware barrier and exposes the basic building blocks of hardware. It also introduces the hard design language, Verilog. Outline * Semiconductors * Transistor switches * Logic Gates text/html 2007-08-31T17:38:28+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/format?rev=1188581908&do=diff Format * Labs The labs focus on technology. They are self-contained and enable you to learn the MIPS assembly and machine languages and explore the CPU datapath and control through Verilog. Labs are meant to be learning instruments, not assessment tools. text/html 2007-08-28T21:46:47+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/forums?rev=1188337607&do=diff Discussion Group A discussion group has been set up for this course. Use it to ask questions related to the course, answer questions posed by others, or discuss course-related issues. * View the discussion group To post a message to the group, you must use one of the following two links (all other posting methods that appear in the group, such as text/html 2007-09-13T19:16:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/foundational_concepts?rev=1189710964&do=diff Foundational Concepts This lecture covers three major topics: The Big Picture (how this course fits in CSE), the Software-Hardware Interface (the Source-to-Execution Journey), and Performance (barriers and innovations). Outline * The view from 40,00 feet text/html 2007-08-28T20:20:57+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/grades?rev=1188332457&do=diff Grades The weight distribution of the course components is as follows: * 00% - Labs A-D * 16% - Lab Test #1 [must complete Labs A-D in order to take this test] * 00% - Labs K-N * 16% - Lab Test #2 [must complete Labs K-N in order to take this test] text/html 2007-08-26T01:53:40+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/labs?rev=1188093220&do=diff The Labs The tasks of each lab can be performed during the first part of your lab session. It is recommended, however, that you perform as many of them as possible before you go to your session as this allows to work at your own pace and leaves time for you to review and/or ask questions. It is important that you fully understand the techniques and concepts that underlie the tasks before attempting the LEx. text/html 2007-10-19T18:50:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/malware_floating-point?rev=1192819850&do=diff Malware and Floating-Point This lecture covers two topics: malicious software and the representation / processing of real numbers. Outline * Self-modifying code * Buffer overrun on the stack and its exploitation. The key idea is to overwrite the return address pushed on the stack. This way, when the method returns, it does not return to the caller but to the location specified by that address. That location has the malicious code. text/html 2007-10-02T18:48:38+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/meet_the_families?rev=1191350918&do=diff Meet the Families This lecture takes a closer look at the instruction families. In addition to examining syntactical issues (such as allowed addressing modes and immediate sizes), we also study the implied algorithms (i.e. how the CPU executes the instruction). Furthermore, we also explore design choices by asking why certain instructions were (or were not) added to the ISA. text/html 2007-10-05T21:01:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/memory_m_l?rev=1191618110&do=diff Memory and M/L This lecture covers memory segments, memory variables, memory instructions, the role of the stack, and machine language (M/L). Outline * The Memory Map * Declaration of Variables in .data * The Load/Store Family * Spilling Data to the stack text/html 2007-11-23T20:45:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/pipelines?rev=1195850704&do=diff Pipelining This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU not by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is also text/html 2007-11-01T21:21:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/resources?rev=1193952096&do=diff Resources * The Resource Directory (code from lecture) * SPIM: the MIPS simulator for Windows. For for other platforms, see this site. * Icarus: the Verilog Compiler for Windows. Unzip to c:\iverilog and include c:\iverilog\bin in your path. To set the path, use the Control Panel or run c:\iverilog\setup every time you open a DOS console. To download this software for other platforms, see text/html 2024-03-08T14:02:31+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/sidebar?rev=1709906551&do=diff * Announcements * Format * Calendar * Labs * Assessment * Discussion Group * Grades * Resources text/html 2007-11-18T19:05:05+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/start?rev=1195412705&do=diff COMPUTER ORGANIZATION Description CSE2021 is a unique course in that it bridges the gap between software (S/W) and hardware (H/W) and exposes the roles played by the operating system (O/S) and the digital logic (D/L) circuits. It relies on a hierarchy of abstractions to present the material in layers, switching roles from text/html 2007-12-01T20:21:27+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/tests?rev=1196540487&do=diff Assessment As indicated in the Grades page, assessment in this course is based on performing eight pass/fail labs and taking four tests and an exam. The four tests are held during the term at the dates specified in the Calendar page. The exam is held during the final examination period at a date/place set by the Registrar Office. This page provides information about the tests and the exam in term of policies, scope, and outline. text/html 2007-11-16T07:15:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/the_multi-cycle_cpu?rev=1195197356&do=diff The Multi-Cycle CPU This lecture covers the design and implementation of the MIPS CPU using a multi-cycle approach. This implementation addresses the two main faults of the single-cycle CPU by eliminating hardware redundancy on the chip and starting the next instruction immediately after the current one completes its execution (rather than waiting a fixed amount of time based on the slowest instruction). text/html 2007-11-09T17:22:13+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/the_single_cycle_cpu?rev=1194628933&do=diff The Single-Cycle CPU This lecture covers the design and implementation of the MIPS CPU using a single-cycle approach. Albeit slow, this implementation is very simple and clean and allows us, once we understand it, to explore more sophisticated approaches. text/html 2007-11-16T01:29:52+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/verilog_modules?rev=1195176592&do=diff Verilog Modules So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. Outline A Verilog top-level (i.e. main) module consists of the following section: * A module text/html 2007-12-17T18:54:11+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2007-08/F/2021/whats_new?rev=1197917651&do=diff Announcements New announcements will be posted here in reverse chronological order. ---------- Mon Dec. 17, 07 * The overall grades are available on ePost. ---------- Mon Dec. 10, 07 * The results of LabTest #2 are available on ePost and so are the reappraisals of Test #2.