CSE2021
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/
2026-04-04T22:55:11+00:00CSE2021
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/_media/wiki:dokuwiki-128.pngtext/html2007-09-23T18:50:21+00:00Anonymous (anonymous@undisclosed.example.com)Assembly Language
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/assembly_language?rev=1190573421&do=diff
Assembly Language
This lecture covers Program Execution (a closer look at DRAM, the CPU, and the fetch-execute cycle) and introduces assembly language. The SPIM simulator is used to demonstrate writing and running programs for the MIPS family of processors.text/html2007-11-24T21:21:24+00:00Anonymous (anonymous@undisclosed.example.com)Caches
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/caches?rev=1195939284&do=diff
Caches
Caching is a technique for improving the performance of any process if the process is likely to be executed more than once. It is used for example by browsers to speed up access to web pages when they are re-visited. It is also used by RAID controllers to speed up access to disk, by TLBs to speed up the virtual-to-physical address translation, and by CPUs to speed up DRAM access. This lecture explores the concepts that underlie caching. It covers single versus multi-word blocks, direct-m…text/html2010-02-13T17:48:47+00:00Anonymous (anonymous@undisclosed.example.com)Calendar
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/calendar?rev=1266083327&do=diff
Calendar
Lecture Notes
WEEK OF Lab Topic Jan 04 ✘ Overview of the course and Performance Jan 11 ✘ Data Translation Jan 18 Lab A Code Translation Jan 25 Lab B Translating Utility Classes -- The Stack Feb 01 Lab Ctext/html2007-08-01T13:57:34+00:00Anonymous (anonymous@undisclosed.example.com)Contact
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/contact?rev=1185976654&do=diff
Contact
Course Director
* Bob J. Smith
* Office: CSE 999 (Computer Science and Engineering Building)
* Phone: (416) 736-2100 x. 11111
* Email: bobsmith AT cse DOT yorku DOT ca
You may contact the course director by e-mail at any time.
Teaching Assistantstext/html2007-07-31T19:53:17+00:00Anonymous (anonymous@undisclosed.example.com)Course Outline
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/course_outline?rev=1185911597&do=diff
Course Outline
The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:
Week 1
Your notes here.
Week 2
Midterm
Drop Deadline
Week 13
Final Examtext/html2007-10-30T17:51:03+00:00Anonymous (anonymous@undisclosed.example.com)Digital Logic
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/digital_logic?rev=1193766663&do=diff
Digital Logic
This lecture crosses the elusive software - hardware barrier and exposes the basic building blocks of hardware. It also introduces the hard design language, Verilog.
Outline
* Semiconductors
* Transistor switches
* Logic Gatestext/html2007-08-01T14:34:50+00:00Anonymous (anonymous@undisclosed.example.com)Frequently Asked Questions
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/faq?rev=1185978890&do=diff
Frequently Asked Questions
Here, you can list frequently asked questions from your students along with responses.
General
Do I need to register for a CSE Computer Account?
Yes.
Do I need to attend class?
If you wish to pass.
Tests
Do I need to write all tests?text/html2009-03-03T18:30:09+00:00Anonymous (anonymous@undisclosed.example.com)Format
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/format?rev=1236105009&do=diff
Format
* Labs
The labs focus on technology. They are self-contained and enable you to learn the MIPS assembly and machine languages and explore the CPU datapath and control through Verilog.
* Lectures
The lectures focus on concepts, principles, and the big-picture. Certain MIPS-specific details are also covered to demonstrate complex ideas or to compare and contrast implementations.text/html2007-08-28T21:46:47+00:00Anonymous (anonymous@undisclosed.example.com)Discussion Group
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/forums?rev=1188337607&do=diff
Discussion Group
A discussion group has been set up for this course. Use it to ask questions related to the course, answer questions posed by others, or discuss course-related issues.
* View the discussion group
To post a message to the group, you must use one of the following two links (all other posting methods that appear in the group, such astext/html2007-09-13T19:16:04+00:00Anonymous (anonymous@undisclosed.example.com)Foundational Concepts
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/foundational_concepts?rev=1189710964&do=diff
Foundational Concepts
This lecture covers three major topics: The Big Picture (how this course fits in CSE), the Software-Hardware Interface (the Source-to-Execution Journey), and Performance (barriers and innovations).
Outline
* The view from 40,00 feettext/html2010-01-13T21:22:19+00:00Anonymous (anonymous@undisclosed.example.com)Grades
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/grades?rev=1263417739&do=diff
Grades
The weight distribution of the course components is as follows:
* 40% - Labs A-D and K-N @5% each
* 25% - Test #1
* 35% - Test #2
You can view your lab marks via
this ePost link.
Your overall course marks are available through
this ePost link.text/html2007-07-31T17:53:24+00:00Anonymous (anonymous@undisclosed.example.com)Important Dates
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/important_dates?rev=1185904404&do=diff
Important Dates
Here, you would list important dates for your course.
* Sept 1 - Assignment 1 Due
* Oct 1 - Course finishedtext/html2009-03-13T04:50:50+00:00Anonymous (anonymous@undisclosed.example.com)The Labs
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/labs?rev=1236919850&do=diff
The Labs
CSE2021Ltext/html2009-04-08T20:38:35+00:00Anonymous (anonymous@undisclosed.example.com)Make-Up Labs
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/labx?rev=1239223115&do=diff
Make-Up Labs
The week after Labs A-D and the one after Labs K-N are designated as lab make-up weeks. During these two weeks, you can attend either (or both) of the Mon and Wed sessions to complete any of the labs that you have not completed yet because of illness or any other reason.text/html2007-10-19T18:50:50+00:00Anonymous (anonymous@undisclosed.example.com)Malware and Floating-Point
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/malware_floating-point?rev=1192819850&do=diff
Malware and Floating-Point
This lecture covers two topics: malicious software and the representation / processing of real numbers.
Outline
* Self-modifying code
* Buffer overrun on the stack and its exploitation. The key idea is to overwrite the return address pushed on the stack. This way, when the method returns, it does not return to the caller but to the location specified by that address. That location has the malicious code.text/html2007-10-02T18:48:38+00:00Anonymous (anonymous@undisclosed.example.com)Meet the Families
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/meet_the_families?rev=1191350918&do=diff
Meet the Families
This lecture takes a closer look at the instruction families. In addition to examining syntactical issues (such as allowed addressing modes and immediate sizes), we also study the implied algorithms (i.e. how the CPU executes the instruction). Furthermore, we also explore design choices by asking why certain instructions were (or were not) added to the ISA.text/html2007-10-05T21:01:50+00:00Anonymous (anonymous@undisclosed.example.com)Memory and M/L
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/memory_m_l?rev=1191618110&do=diff
Memory and M/L
This lecture covers memory segments, memory variables, memory instructions, the role of the stack, and machine language (M/L).
Outline
* The Memory Map
* Declaration of Variables in .data
* The Load/Store Family
* Spilling Data to the stacktext/html2009-03-05T00:47:04+00:00Anonymous (anonymous@undisclosed.example.com)
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/overview_of_the_course?rev=1236214024&do=diff
Course Overview
FIXME
Slidestext/html2007-11-23T20:45:04+00:00Anonymous (anonymous@undisclosed.example.com)Pipelining
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/pipelines?rev=1195850704&do=diff
Pipelining
This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU not by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is alsotext/html2007-07-31T18:55:53+00:00Anonymous (anonymous@undisclosed.example.com)Policies
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/policies?rev=1185908153&do=diff
Policies
Here, you can list specific course policies.
Academic Dishonesty
For more information on Academic Dishonesty, click here.text/html2009-03-18T20:35:54+00:00Anonymous (anonymous@undisclosed.example.com)Resources
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/resources?rev=1237408554&do=diff
Resources
* The Resource Directory (code from lecture)
* SPIM: the MIPS simulator for Windows. For for other platforms, see this site.
* Icarus: the Verilog Compiler for Windows. Unzip to c:\iverilog and include c:\iverilog\bin in your path. To set the path, use the Control Panel or run c:\iverilog\setup every time you open a DOS console. To download this software for other platforms, seetext/html2024-03-08T14:02:31+00:00Anonymous (anonymous@undisclosed.example.com)
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/sidebar?rev=1709906551&do=diff
* Announcements
* Calendar
* Format
* Labs
* Grades
* Discussion Forum
* Policies
* Resourcestext/html2010-01-20T16:46:41+00:00Anonymous (anonymous@undisclosed.example.com)COMPUTER ORGANIZATION
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/start?rev=1264006001&do=diff
COMPUTER ORGANIZATION
Description
CSE2021 is a unique course in that it bridges the gap between software (S/W) and hardware (H/W) and exposes the roles played by the operating system (O/S) and the digital logic (D/L) circuits. It relies on a hierarchy of abstractions to present the material in layers, switching roles fromtext/html2010-03-31T20:49:44+00:00Anonymous (anonymous@undisclosed.example.com)Assessment
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/tests?rev=1270068584&do=diff
Assessment
As indicated in the Grades page, assessment in this course is based on performing eight lab tests and taking two written tests. This page provides information about the first written test.
Written Test #1
Policies
* Test time/place: 5:30-6:45 pm on Monday Feb 22 in VH-Dtext/html2007-07-31T18:42:03+00:00Anonymous (anonymous@undisclosed.example.com)Textbook
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/textbook?rev=1185907323&do=diff
Textbook
You will require the following textbook for this course:
* Jane Doe. Absolute Computing. Second edition. Addison Wesley, 2007.
You may purchase this book through the York University Bookstore.text/html2007-11-16T07:15:56+00:00Anonymous (anonymous@undisclosed.example.com)The Multi-Cycle CPU
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/the_multi-cycle_cpu?rev=1195197356&do=diff
The Multi-Cycle CPU
This lecture covers the design and implementation of the MIPS CPU using a multi-cycle approach. This implementation addresses the two main faults of the single-cycle CPU by eliminating hardware redundancy on the chip and starting the next instruction immediately after the current one completes its execution (rather than waiting a fixed amount of time based on the slowest instruction).text/html2007-11-09T17:22:13+00:00Anonymous (anonymous@undisclosed.example.com)The Single-Cycle CPU
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/the_single_cycle_cpu?rev=1194628933&do=diff
The Single-Cycle CPU
This lecture covers the design and implementation of the MIPS CPU using a single-cycle approach. Albeit slow, this implementation is very simple and clean and allows us, once we understand it, to explore more sophisticated approaches.text/html2007-11-16T01:29:52+00:00Anonymous (anonymous@undisclosed.example.com)Verilog Modules
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/verilog_modules?rev=1195176592&do=diff
Verilog Modules
So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves.
Outline
A Verilog top-level (i.e. main) module consists of the following section:
* A moduletext/html2010-04-19T20:18:09+00:00Anonymous (anonymous@undisclosed.example.com)Announcements
https://wiki.eecs.yorku.ca/course_archive/2009-10/W/2021/whats_new?rev=1271708289&do=diff
Announcements
New announcements will be posted here in reverse chronological order.
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Mon Apr 19, 10
* The marks of Test #2 and the overall letter grades are now on ePost. The letter grades are based on the weighted sum of the three components: Test1, Test2, and Labs. The breakdown of the Labs component is posted under the 2021L course as before. If you suspect errors in your letter grade, take one of the following actions depending on the type of error: If you see an arithmetic e…