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--- course_outline [2009/12/29 16:15] – allison
+++ course_outline [2009/12/30 02:50] – allison
@@ Line 6: / Line 6: @@
 York University,  Toronto, Ontario
-Class meets TR 16:00-17:30 SC 303
-Labs as scheduled by registrar
-  * LAB01 M 13:00-16:00 CSE 1004
-  * LAB02 F 13:00-16:00 CSE 1004 (may be canceled)
-Instructor :  Robert Allison, CSE 3051, allison@cse.yorku.ca, 416-736-2100 x20192
-office hours: TBD.
-TA: Cyrus Minwalla.
+[[https://w2prod.sis.yorku.ca/Apps/WebObjects/cdm.woa/34/wo/RBHo4bO8mxAEcxUbcf11l0/3.1.8.17|Fall/Winter 2009-2010 Schedule]]
+====== Contact ======
+[[contact | Instructor: R. Allison; TA: Cyrus Minwalla]]
 ====== Overview ======
@@ Line 28: / Line 28: @@
 ====== Topics (tentative) ======
+^  Week  ^  Dates  ^  Lecture  ^  Lab  ^
+| 1  | Jan 5, 7 | Introduction  | No lab  |
+| 2  | Jan 12, 14  | microcontrollers, 68HCS12 architecture and instruction set | Lab 0 (Safety Issues, Introduction to Facilities and Tutorial  |
+| 3  | Jan 19, 21  | Peripherals  | Lab 1  |
+| 4  | Jan 26, 28  | Interrupts  | Lab 2  |
+| 5  | Feb 2, 4 | Test #1 Mar 31, Peripherals & Interrupts  | Lab 3  |
+| 6  | Feb 9, 11   | Memory and Busses   | Lab 3 con't   |
+|    | Feb 16, 18  | READING WEEK  | No lab  |
+| 7  | Feb 23, 25  | Interfacing  | Lab 4  |
+| 8  | Mar 2, 4   | Interfacing  | Lab 4  |
+| 9  | Mar 9, 11   | Analogue interfacing, Test #2 Apr 28  | Lab 5  |
+| 10  | Mar 16, 18   | Programmable Logic and Rapid prototyping using FPGAs  |Lab 5 con't  |
+| 11  | Mar 23, 25   | Power, High Speed and other design constraints (time permitting)  | Lab 6  |
+| 12  | Mar 30, Apr 1   | Power, High Speed and other design constraints (time permitting)  | Lab 6  |
+| 13  | Apr 5   | no class  | Lab 6  |
-Week 1:
-Dates
-Lecture
-Lab
-March 5
-Introduction
-No lab
-Mar 10, 12
-microcontrollers, 68HCS12 architecture and instruction set
-Lab 0 (Safety Issues, Introduction to Facilities and Tutorial
-Mar 17, 19
-Peripherals
-Lab 1
-Mar 24, 26
-Interrupts
-Lab 2
-Mar 31, Apr 2
-Test #1 Mar 31, Peripherals & Interrupts
-Lab 3
-Apr 7, 9
-Memory and Busses
-Lab 3 con't
-Apr 14, 16
-Interfacing
-Lab 4
-Apr 21,23
-Interfacing
-Lab 4
-Apr 28, 30
-Analogue interfacing, Test #2 Apr 28
-Lab 5
-May 5, 7
-Programmable Logic and Rapid prototyping using FPGAs
-Lab 5 con't
-May 12, 14
-Power, High Speed and other design constraints (time permitting)
-Lab 6
-May 19
-Test #3 May 19
-Lab 6 on May 20 (treated as Monday, May 18 is Victoria Day holiday)
-Note May 18 is a Stat. Holiday.
 ====== Evaluation ======
+[[grades| Grades and Grading]]
-Components will be given a letter grade mark and then combined to give an overall mark. Numeric marks, when used, will be converted to a letter grade using the standard departmental conversion table.
-Classroom participation 8%
-Tests            48%
-Labs            44% (Lab 1,2 worth 6 marks each, Labs 3-6 worth 8 marks each)
-All course components, labs, test and final, are required. Labs and the midterm may only be missed for approved medical reasons. Under these conditions weighting will be redistributed by increasing weighting of the final exam.
-Students are responsible for all material covered in the lectures, labs and required readings. There is a significant amount of readings for this course.  Students are expected to become proficient in Verilog synthesis and microcontroller programming outside of class hours.
-====== Text ======
-The required textbook for this course is available from the bookstore:
-• Wayne Wolf, Computers As Components, Second Edition, Morgan Kaufmann, ISBN: 0-12-374397-8, 2008
-Recommended text (also on reserve at library)
-• Michael D. Ciletti, Advanced Digital Design with the VERILOG (TM) HDL, 1/e, Prentice-Hall, ISBN 0-13-089161-4.
 ====== Laboratory ======
@@ Line 207: / Line 61: @@
-====== Course Outline ======
-The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:
-===== Week 1 =====
-Your notes here.
-===== Week 2 =====
-===== Midterm =====
-===== Drop Deadline =====
-===== Week 13 =====
-===== Final Exam =====