course_outline
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| course_outline [2009/12/30 02:33] – allison | course_outline [2009/12/30 02:50] – allison | ||
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| York University, | York University, | ||
| - | Class meets TR 16:00-17:30 SC 303 | ||
| - | Labs as scheduled by registrar | ||
| - | * LAB01 M 13:00-16:00 CSE 1004 | ||
| - | * LAB02 F 13:00-16:00 CSE 1004 (may be canceled) | ||
| - | Instructor : Robert Allison, CSE 3051, allison@cse.yorku.ca, | ||
| - | office hours: TBD. | ||
| - | TA: Cyrus Minwalla. | + | [[https:// |
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| + | ====== Contact ====== | ||
| + | |||
| + | [[contact | Instructor: R. Allison; | ||
| ====== Overview ====== | ====== Overview ====== | ||
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| | 10 | Mar 16, 18 | Programmable Logic and Rapid prototyping using FPGAs |Lab 5 con' | | 10 | Mar 16, 18 | Programmable Logic and Rapid prototyping using FPGAs |Lab 5 con' | ||
| | 11 | Mar 23, 25 | Power, High Speed and other design constraints (time permitting) | | 11 | Mar 23, 25 | Power, High Speed and other design constraints (time permitting) | ||
| - | | 12 | Mar 30, 1 | Power, High Speed and other design constraints (time permitting) | + | | 12 | Mar 30, Apr 1 | Power, High Speed and other design constraints (time permitting) |
| - | | 13 | Mar 30, 1 | Power, High Speed and other design constraints (time permitting) | + | | 13 | Apr 5 | no class | Lab 6 | |
| ====== Evaluation ====== | ====== Evaluation ====== | ||
| - | [[grades]] | + | [[grades| Grades and Grading]] |
course_outline.txt · Last modified: 2009/12/30 13:35 by allison