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--- important_dates [2010/12/11 09:42] – asif
+++ important_dates [2010/12/19 04:45] (current) – asif
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 ====== Important Dates ======
+== Final Exam ==
+  * Rescheduled Date: Thu, Dec. 23, 2010 (7:00pm - 10:00pm) Location: CLH A\\
+** Instructions for Final: ** \\
+__General__
+  * The exam is closed-book, 3-hour long.
+  * You must bring a photo ID.
+  * You may use a pen or a pencil. Unlike the midterm, answers written in pencil can be re-marked.
+  * You may not use cell phones or any computing or communication device during the exam with the exception of a non-programmable calculator.
+  * You may bring one information sheet (8.5"x11"-both sides). Note, however, that we will provide the MIPS instruction data sheet and, if needed, the datapath figures (for the single-cycle, multicycle, and pipelined processor) and the finite state machine diagram for multi-cycle control.
+  * Unless stated otherwise, you must justify or explain your answers; i.e. it is not enough to put down an answer. In fact, answers with little or no explanation will receive little or no marks even if correct
+__Scope__
+  * All material covered in the course. The exam is comprehensive covering all material covered in the course.
+  * You will not be responsible for Verilog on the examination
+  * The exam will cover the sections specified in the handouts.
+__Outline__
+Six groups of questions:\\
+A. On assembly language and the topics covered in the labs (MIPS)\\
+B. On the datapath/control of the single-cycle processor\\
+C. On the multi-cycle processor and its control\\
+D. On pipelining, hazards, and hazard avoidance\\
+E. On foundational concepts; i.e. write a logical argument (to show that a given idea is correct or incorrect) or perform a computation\\
+F. ALU Design
+Note that the questions on the the single cycle, multicycle and pipeline machines will be meant to test your understanding of the datapath and its controls. So you may have questions that give you the datapath and the control lines and then propose a particular MIPS statement or sequence of statements and ask what data flows in the datapath at particular points or what controls are set and what data will be stored in registers or Main memory or in buffers. We might also ask what would happen if the controls are set incorrectly. Or, inversely you may be given data that flows in the lines of some of the data path or the control signals that are set and then asked what MIPS instruction or sequence of MIPS instructions could be responsible for the flow. In the multicycle machine we may ask questions about the FSM settings or sequences. For the pipeline machine you may be asked simple questions about hazards and how they affect the instruction delays, or questions about how to eliminate delays in certain situations. You could be asked simple questions about performance and the comparison of performance among the types of machines.
 == Labtest ==
   * Sep 27, 2010 (7:00 - 10:00 p.m.): Labtest A for Lab Section 01.
@@ Line 15: / Line 44: @@
 == Drop date ==
   * Nov. 12, 2010: Last date to drop the course without a grade.
-== Final Exam ==
-  * Tuesday, Dec 14, 2010 (7:00pm - 10:00pm)
-** Instructions for midterm: ** \\
-  - General
-  * The exam is closed-book, 3-hour long.
-  * You must bring a photo ID.
-  * You may use a pen or a pencil. Unlike the midterm, answers written in pencil can be re-marked.
-  * You may not use cell phones or any computing or communication device during the exam with the exception of a non-programmable calculator.
-  * You may bring one information sheet (8.5"x11"-both sides). Note, however, that we will provide the MIPS instruction data sheet and, if needed, the datapath figures (for the single-cycle, multicycle, and pipelined processor) and the finite state machine diagram for multi-cycle control.
-  * Unless stated otherwise, you must justify or explain your answers; i.e. it is not enough to put down an answer. In fact, answers with little or no explanation will receive little or no marks even if correct
-  - Scope
-  * All material covered in the course. The exam is comprehensive covering all material covered in the course.
-  * You will not be responsible for Verilog on the examination
-  - Outline
-Five groups of questions:
-   A. On assembly language and the topics covered in the labs (MIPS)\\
-   B. On the datapath/control of the single-cycle processor\\
-   C. On the multi-cycle processor and its control\\
-   D. On pipelining, hazards, and hazard avoidance\\
-   E. On foundational concepts; i.e. write a logical argument (to show that a given idea is correct or incorrect) or perform a computation
-   F. ALU Design
-    * The question on the the single cylce, multicylce and pipeline machines will be meant to test your understanding of the datapath and its controls. so you may have questions that give you the datapath and the control lines and then propose a particular MIPS statement or sequence of statements and ask what data flows in the datapath at particular points or what controls are set and what data will be stored in registers or Main memory or in buffers. We might also ask what would happen if the controls are set incorrectly. Or inversely you may be given data that flows in the lines of some of the data path or the cotrol signals that are set and then asked what MIPS instruction or sequence of MIPS instructions could be responsible for the flow. In the multicylce machine we may ask questions about the FSM settings or sequences. For the pipeliine machine you may be asked simple questions about hazards and how they affect the instruction delays, or questions about how to eliminate delays in certain situations. You could be asked simple questions about performance and the comparison of performnce among the types of machines.
-    * Again the questions for cache will again be maent to test your understanding. You may be asked about the implementation of the direct addressing cache or about the calculation of cache sizing.