important_dates
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| important_dates [2010/12/11 09:50] – asif | important_dates [2010/12/19 04:45] (current) – asif | ||
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| ====== Important Dates ====== | ====== Important Dates ====== | ||
| == Final Exam == | == Final Exam == | ||
| - | * Tuesday, Dec 14, 2010 (7:00pm - 10:00pm) | + | * Rescheduled Date: Thu, Dec. 23, 2010 (7:00pm - 10: |
| ** Instructions for Final: ** \\ | ** Instructions for Final: ** \\ | ||
| __General__ | __General__ | ||
| Line 13: | Line 13: | ||
| __Scope__ | __Scope__ | ||
| * All material covered in the course. The exam is comprehensive covering all material covered in the course. | * All material covered in the course. The exam is comprehensive covering all material covered in the course. | ||
| - | * You will not be responsible for Verilog on the examination | + | * You will not be responsible for Verilog on the examination |
| + | * The exam will cover the sections specified in the handouts. | ||
| + | |||
| __Outline__ | __Outline__ | ||
| + | |||
| Six groups of questions: | Six groups of questions: | ||
| A. On assembly language and the topics covered in the labs (MIPS)\\ | A. On assembly language and the topics covered in the labs (MIPS)\\ | ||
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