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| Computers are usually viewed as having a structure organized into several levels, ranging from high-level programming languages such as Java to digital logic circuits. Each level provides specific resources and abstractions for the programmer. The course provides students with the basic understanding of the computers at the low-lying levels of this structure. This includes programming in assembly and machine language, computer organization (CPU, DRAM, I/O, and buses), CPU structure (Datapath and Control), and digital logic. The presentation is centered on performance and covers topics like caching, pipelining, and parallel processing. The course presents theoretical concepts as well as concrete implementations on a modern, RISC processor. The following topics are covered in the course. | Computers are usually viewed as having a structure organized into several levels, ranging from high-level programming languages such as Java to digital logic circuits. Each level provides specific resources and abstractions for the programmer. The course provides students with the basic understanding of the computers at the low-lying levels of this structure. This includes programming in assembly and machine language, computer organization (CPU, DRAM, I/O, and buses), CPU structure (Datapath and Control), and digital logic. The presentation is centered on performance and covers topics like caching, pipelining, and parallel processing. The course presents theoretical concepts as well as concrete implementations on a modern, RISC processor. The following topics are covered in the course. | ||
| - | 1. Computer Organization and Performance | + | 1. Computer Organization and Performance\\ |
| - | 2. Assembly Language Programming (MIPS) | + | 2. Assembly Language Programming (MIPS)\\ |
| - | 3. Machine Language, SPIM simulator. | + | 3. Machine Language, SPIM simulator.\\ |
| - | 4. Data Representation | + | 4. Data Representation\\ |
| - | 5. Hardware abstraction through Verilog | + | 5. Hardware abstraction through Verilog\\ |
| - | 6. ALU: Datapath and Control. | + | 6. ALU: Datapath and Control.\\ |
| - | 7. Datapath and Control (Single cycle and multiple cycles). | + | 7. Datapath and Control (Single cycle and multiple cycles).\\ |
| - | 8. Pipelines | + | 8. Pipelines\\ |
| 9. Caches | 9. Caches | ||
| - | In addition, the lab would introduce the students to Verilog | + | SPIM, a MIPS programming simulator, and Verilog, a hardware description language used to design electronic systems, will be introduced to the students in the lab. |
| - | + | ||
| - | ===== Textbook ===== | + | |
| - | + | ||
| - | M. Mandal and A. Asif, // | + | |
| ===== Lectures ===== | ===== Lectures ===== | ||
| - | * Tuesdays | + | * Mondays |
| ===== Labs ===== | ===== Labs ===== | ||
| - | * Mondays, | + | * Mondays, |
| - | * Fridays, 1:30pm - 4:30pm, CSE 3057 | + | * Tuesdays, 7:00pm - 10:00pm, CSE 1006 |
start.1284052048.txt.gz · Last modified: 2010/09/09 17:07 by asif