Differences

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--- format [2007/08/28 20:35] – created roumani
+++ format [2011/01/25 16:19] (current) – roumani
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-====== Format ======
+===== Expected Learning Outcomes =====
+By the end of the course, you are expected to be able to:
+  * Translate a given high-level program to assembly/machine language
+    * Represent numbers, characters, and other forms of data in binary
+    * Express logic using assembly language instructions
+    * Utilize registers, the stack, the heap, and the data segment to store data
+    * Encode assembly language instructions in machine language format
+  * Build a CPU out of basic building blocks such as gates and flip-flops
+    * Build the ALU using gates and Verilog
+    * Design the CPU's datapath and control
+    * Implement a pipeline and handle its hazards
+    * Augment the CPU with a cache
+  * Assess the end-to-end performance
+    * Identify the key performance drivers and their physical limits
+    * Compare and contrast the RISC and CISC approaches
+    * Compute the throughput of a pipelined CPU for a given code fragment
+    * Analyze the effect of a cache of a given specs on the system's performance
-=== Labs ===
-The labs focus on technology. They are self-contained and enable you to learn the MIPS assembly/machine language and explore CPU design through Verilog.