verilog_modules

This is an old revision of the document!

Table of Contents

Verilog Modules
- Outline
- To Do

Verilog Modules

So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves.

Outline

Performing PC+4 using the main ALU
Performing PC+4 + 4*Label using the main ALU
Adding registers to hold intermediate data
Combining the two memory units
Issuing the control signals for State #0
Doing something useful in State #1
Instruction-dependent states

To Do

Look at the program alu1b and its tester alu1bClient in the Resource Directory. alu1b is a 1-bit adder component made up of basic gates.

Look at the program alu2b and its tester alu2bClient in the Resource Directory. alu2b is a 2-bit adder component made up of two alu1b adders.

verilog_modules.1195176101.txt.gz · Last modified: 2007/11/16 01:21 by roumani