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--- whats_new [2011/07/16 07:17] – skhan
+++ whats_new [2011/08/03 01:57] – skhan
@@ Line 3: / Line 3: @@
 New announcements will be posted here in reverse chronological order.
+----
+**Tue Aug 2, 2011**
+  *For the Verilog part of the exam, please review all four Verilog labs.
+----
+**Mon Aug 1, 2011**
+  *Additional office hours for this week: Wed August 3, 4:00-6:00 pm.
+  *The final exam will be a closed book, 180-min test covering everything that was covered after the midterm; i.e. the five topics: floating-point, Verilog, single-cycle, pipelines, and caches. Bring a photo ID and optionally a calculator and an information sheet (one 8.5×11” sheet on which you can write or type on either side). Note that the MIPS Green Card, the SPIM system call table, and the CPU diagrams will be provided.
+----
+**Fri July 22, 2011**
+  *To clarify, the marking scheme for the labs is as follows:
+  - If you have attempted all 8 labs, then york marks for the labs = your best 7 lab marks + your best lab mark
+  - If you have attempted 7 labs, then york marks for the labs = your marks for the 7 labs that you have done + your best lab mark
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