Differences

This shows you the differences between two versions of the page.

--- course_outline [2009/12/30 02:21] – allison
+++ course_outline [2011/01/02 19:36] (current) – allison
@@ Line 6: / Line 6: @@
 York University,  Toronto, Ontario
-Class meets TR 16:00-17:30 SC 303
-Labs as scheduled by registrar
-  * LAB01 M 13:00-16:00 CSE 1004
-  * LAB02 F 13:00-16:00 CSE 1004 (may be canceled)
-Instructor :  Robert Allison, CSE 3051, allison@cse.yorku.ca, 416-736-2100 x20192
-office hours: TBD.
-TA: Cyrus Minwalla.
+[[https://w2prod.sis.yorku.ca/Apps/WebObjects/cdm.woa/11/wo/jbfEnQdqTGKm6NatTt8L5w/3.1.9.8.1.0.0.5|Fall/Winter 2010-2011 Schedule]]
+====== Contact ======
+[[contact | Instructor: R. Allison; TA: Anthony Calce, Cyrus Minwalla]]
 ====== Overview ======
@@ Line 29: / Line 29: @@
 ^  Week  ^  Dates  ^  Lecture  ^  Lab  ^
-| 1  |  Jan 5, 7 |  Introduction  |  No lab  |
+| 1  | Jan 4, 6 | Introduction  | No lab  |
-| 2  |  Jan 12, 14  |  microcontrollers, 68HCS12 architecture and instruction set |  Lab 0 (Safety Issues, Introduction to Facilities and Tutorial  |
+| 2  | Jan 11, 13  | Microcontrollers, 68HCS12 architecture and instruction set | Lab 0 (Safety Issues, Introduction to Facilities and Tutorial  |
-|  3  |  Jan 19, 21  |  Peripherals  |  Lab 1  |
+| 3  | Jan 18, 20  | Peripherals  | Lab 1  |
-|  4  |  Jan 26, 28  |  Interrupts  |  Lab 2  |
+| 4  | Jan 25, 27  | Interrupts  | Lab 2  |
-|  5  |  Feb 2, 4 |  Test #1 Mar 31, Peripherals & Interrupts  |  Lab 3  |
+| 5  | Feb 1, 3 | Peripherals & Interrupts  | Lab 3  |
-|  6  |  Feb 9, 11   |  Memory and Busses   |  Lab 3 con't   |
+| 6  | Feb 8, 10   | Memory and Busses   | Lab 3 con't   |
-|  7
+| 7  | Feb 15, 17  | Interfacing  | Lab 4  |
+|    | Feb 22, 24  | READING WEEK  | No lab  |
+| 8  | Mar 1, 3   | Interfacing  | Lab 4  |
+| 9  | Mar 8, 10   | Analogue interfacing  | Lab 5  |
+| 10  | Mar 15, 17   | Programmable Logic and Rapid prototyping using FPGAs  |Lab 5 con't  |
+| 11  | Mar 22, 24   | Power, High Speed and other design constraints (time permitting)  | Lab 6  |
+| 12  | Mar 29, 31   | Power, High Speed and other design constraints (time permitting)  | Lab 6  |
-Interfacing
-Lab 4
-Interfacing
-Lab 4
-Analogue interfacing, Test #2 Apr 28
-Lab 5
-Programmable Logic and Rapid prototyping using FPGAs
-Lab 5 con't
-Power, High Speed and other design constraints (time permitting)
-Lab 6
-Test #3 May 19
-Lab 6 on May 20 (treated as Monday, May 18 is Victoria Day holiday)
+Quizzes will be held during class periods.
 ====== Evaluation ======
-[[grades]]
+[[grades| Grades and Grading]]
@@ Line 141: / Line 54: @@
 ====== Laboratory ======
-A mandatory hardware laboratory component is required for COSC3215 (this is why the course has 4 credit weighting). The laboratory is weekly and requires attendance during the student's lab session. If you cannot attend your lab session you will not be able to continue in the course. Students will work in pairs.
+[[laboratory:start| Lab information]]
-Labs require preparatory work, which must be completed and approved prior to starting the lab. YOU WILL NOT BE ALLOWED TO START THE LAB IF YOU HAVE NOT SUBMITTED COMPLETE PREPATORY WORK. Students are required to document their lab work in their lab notebooks and with other appropriate documentation. This includes documenting all data collected and answering all questions posed. Students must present the documentation, answer questions about their approach, and demo their lab to the TA at the end of the lab session. Final documentation including all code and design documents should be electronically submitted using the ‘submit’ facility on Prism within 24 hours following the end of the lab session.
-The laboratory is hands on and students should have experience with electronic circuits, computer organization and digital logic (e.g. strongly recommended or prerequisite courses are Phys 3150, COSC 2021, COSC 3201).