https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/ 2026-04-07T18:14:58+00:00 https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/ https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/_media/wiki:dokuwiki-128.png text/html 2007-09-23T18:50:21+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/assembly_language?rev=1190573421&do=diff Assembly Language This lecture covers Program Execution (a closer look at DRAM, the CPU, and the fetch-execute cycle) and introduces assembly language. The SPIM simulator is used to demonstrate writing and running programs for the MIPS family of processors. text/html 2007-11-24T21:21:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/caches?rev=1195939284&do=diff Caches Caching is a technique for improving the performance of any process if the process is likely to be executed more than once. It is used for example by browsers to speed up access to web pages when they are re-visited. It is also used by RAID controllers to speed up access to disk, by TLBs to speed up the virtual-to-physical address translation, and by CPUs to speed up DRAM access. This lecture explores the concepts that underlie caching. It covers single versus multi-word blocks, direct-m… text/html 2012-11-25T02:31:09+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/calendar?rev=1353810669&do=diff Calendar WEEK # WEEK OF Mon Wed Lab Approximate Lecture Schedule 1 Sep 03 - ✔ - Overview of the course 2 Sep 10 ✔ ✔ - Performance and Data Translation 3 Sep 17 ✔ ✔ A Code Translation text/html 2007-08-01T13:57:34+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/contact?rev=1185976654&do=diff Contact Course Director * Bob J. Smith * Office: CSE 999 (Computer Science and Engineering Building) * Phone: (416) 736-2100 x. 11111 * Email: bobsmith AT cse DOT yorku DOT ca You may contact the course director by e-mail at any time. Teaching Assistants text/html 2007-07-31T19:53:17+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/course_outline?rev=1185911597&do=diff Course Outline The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed: Week 1 Your notes here. Week 2 Midterm Drop Deadline Week 13 Final Exam text/html 2007-10-30T17:51:03+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/digital_logic?rev=1193766663&do=diff Digital Logic This lecture crosses the elusive software - hardware barrier and exposes the basic building blocks of hardware. It also introduces the hard design language, Verilog. Outline * Semiconductors * Transistor switches * Logic Gates text/html 2007-08-01T14:34:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/faq?rev=1185978890&do=diff Frequently Asked Questions Here, you can list frequently asked questions from your students along with responses. General Do I need to register for a CSE Computer Account? Yes. Do I need to attend class? If you wish to pass. Tests Do I need to write all tests? text/html 2011-09-27T12:47:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/format?rev=1317127624&do=diff Format * Labs The labs focus on technology. They are self-contained and enable you to learn the MIPS assembly and machine languages and explore the CPU datapath and control through Verilog. * Lectures The lectures focus on concepts, principles, and the big-picture. Certain MIPS-specific details are also covered to demonstrate complex ideas or to compare and contrast implementations. text/html 2007-08-28T21:46:47+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/forums?rev=1188337607&do=diff Discussion Group A discussion group has been set up for this course. Use it to ask questions related to the course, answer questions posed by others, or discuss course-related issues. * View the discussion group To post a message to the group, you must use one of the following two links (all other posting methods that appear in the group, such as text/html 2007-09-13T19:16:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/foundational_concepts?rev=1189710964&do=diff Foundational Concepts This lecture covers three major topics: The Big Picture (how this course fits in CSE), the Software-Hardware Interface (the Source-to-Execution Journey), and Performance (barriers and innovations). Outline * The view from 40,00 feet text/html 2011-11-07T21:13:00+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/grades?rev=1320700380&do=diff Grades The weight distribution of the course components is as follows: * 32% - Labs A-D and K-N @4% each * 20% - Midterm * 12% - 3 Quizzes @4% each * 36% - Final Exam You can view your marks on: ePost Conversion from numeric to letter grade is applied to the overall mark only and in accordance with the following departmental standard: text/html 2007-07-31T17:53:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/important_dates?rev=1185904404&do=diff Important Dates Here, you would list important dates for your course. * Sept 1 - Assignment 1 Due * Oct 1 - Course finished text/html 2011-09-27T12:49:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/labs?rev=1317127798&do=diff The Labs The Labs for the course can be accessed: CSE2021L Marks are available on 2021L ePost text/html 2011-10-24T19:49:54+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/labx?rev=1319485794&do=diff Make-Up Labs The week after Labs A-D and the one after Labs K-N are designated as lab make-up weeks. During these two weeks, you can attend either (or both) of the Mon and Tue sessions to complete any of the labs that you have not completed yet because of illness or any other reason. text/html 2012-12-05T04:42:00+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/lectures?rev=1354682520&do=diff Lecture Notes Week 1 - Sep 03 [Wednesday] Week 2 - Sep 10 [Monday] [Wednesday] Week 3 - Sep 17 [Monday] [Wednesday] Week 4 - Sep 24 [Monday] Wednesday - Quiz 1 Week 5 - Oct 01 [Monday] [Wednesday] Week 6 - Oct 08 Monday: Thanksgiving Wednesday (Midterm) Week 7 - Oct 15 [Monday] [Wednesday] Week 8 - Oct 22 [Monday] text/html 2007-10-19T18:50:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/malware_floating-point?rev=1192819850&do=diff Malware and Floating-Point This lecture covers two topics: malicious software and the representation / processing of real numbers. Outline * Self-modifying code * Buffer overrun on the stack and its exploitation. The key idea is to overwrite the return address pushed on the stack. This way, when the method returns, it does not return to the caller but to the location specified by that address. That location has the malicious code. text/html 2007-10-02T18:48:38+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/meet_the_families?rev=1191350918&do=diff Meet the Families This lecture takes a closer look at the instruction families. In addition to examining syntactical issues (such as allowed addressing modes and immediate sizes), we also study the implied algorithms (i.e. how the CPU executes the instruction). Furthermore, we also explore design choices by asking why certain instructions were (or were not) added to the ISA. text/html 2007-10-05T21:01:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/memory_m_l?rev=1191618110&do=diff Memory and M/L This lecture covers memory segments, memory variables, memory instructions, the role of the stack, and machine language (M/L). Outline * The Memory Map * Declaration of Variables in .data * The Load/Store Family * Spilling Data to the stack text/html 2009-03-05T00:47:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/overview_of_the_course?rev=1236214024&do=diff Course Overview FIXME Slides text/html 2007-11-23T20:45:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/pipelines?rev=1195850704&do=diff Pipelining This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU not by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is also text/html 2007-07-31T18:55:53+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/policies?rev=1185908153&do=diff Policies Here, you can list specific course policies. Academic Dishonesty For more information on Academic Dishonesty, click here. text/html 2012-10-18T21:27:26+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/resources?rev=1350595646&do=diff Resources * SPIM Simulator (PCSpim or QtSpim) - For all platforms, see this site. * Icarus: the Verilog Compiler for Windows. Download version 0.9.4 (use the setup.exe provided) and install to c:\iverilog, ensure that the path variable is modified, since you will be running it from a DOS shell. To download this software for other platforms, see text/html 2024-03-08T14:02:31+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/sidebar?rev=1709906551&do=diff * Announcements * Calendar * Format * Lecture Notes * Labs * Grades * Policies * Resources text/html 2012-10-10T23:50:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/start?rev=1349913015&do=diff COMPUTER ORGANIZATION Fall 2012 Description CSE2021 explores how a processor's hardware and software interact to accomplish a given computational task. Our description of the inner workings of a computer will use an hierarchy of abstractions. We will follow the journey of instructions from high-level to assembly and machine code, through RAM and caches, to the logic circuits within the CPU core that make up the computer's datapath and control elements. Lecture material is supplemented with l… text/html 2007-12-01T20:21:27+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/tests?rev=1196540487&do=diff Assessment As indicated in the Grades page, assessment in this course is based on performing eight pass/fail labs and taking four tests and an exam. The four tests are held during the term at the dates specified in the Calendar page. The exam is held during the final examination period at a date/place set by the Registrar Office. This page provides information about the tests and the exam in term of policies, scope, and outline. text/html 2007-07-31T18:42:03+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/textbook?rev=1185907323&do=diff Textbook You will require the following textbook for this course: * Jane Doe. Absolute Computing. Second edition. Addison Wesley, 2007. You may purchase this book through the York University Bookstore. text/html 2007-11-16T07:15:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/the_multi-cycle_cpu?rev=1195197356&do=diff The Multi-Cycle CPU This lecture covers the design and implementation of the MIPS CPU using a multi-cycle approach. This implementation addresses the two main faults of the single-cycle CPU by eliminating hardware redundancy on the chip and starting the next instruction immediately after the current one completes its execution (rather than waiting a fixed amount of time based on the slowest instruction). text/html 2007-11-09T17:22:13+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/the_single_cycle_cpu?rev=1194628933&do=diff The Single-Cycle CPU This lecture covers the design and implementation of the MIPS CPU using a single-cycle approach. Albeit slow, this implementation is very simple and clean and allows us, once we understand it, to explore more sophisticated approaches. text/html 2007-11-16T01:29:52+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/verilog_modules?rev=1195176592&do=diff Verilog Modules So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. Outline A Verilog top-level (i.e. main) module consists of the following section: * A module text/html 2012-12-08T14:43:08+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2012-13/F/2021/whats_new?rev=1354977788&do=diff Announcements New announcements will be posted here in reverse chronological order. --- Sat Dec 08, 2012 * The TA tells me that Quiz 3's will be ready on Monday for pick-up. I leave them with the CSE Main Office (LAS 1003) for pick-up in the afternoon.