CSE3201 https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/ 2026-04-06T02:47:33+00:00 CSE3201 https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/ https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/_media/wiki:dokuwiki-128.png text/html 2012-11-30T06:17:37+00:00 allison (allison@undisclosed.example.com) Assignments https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/assignments:start?rev=1354256257&do=diff Assignments Suggested assignments: * Chapter 2: 2.1-2.5, 2.7, 2.10, 2.12, 2.18-2.20, 2.27-2.29, 2.38-2.40, 2.42, 2.48-2.50 * Chapter 4: 4.1-4.6, 4.9, 4.11, 4.12, 4.14-4.17, 4.20, 4.21, 4.35-4.38 * Chapter 5: 5.3, 5.4, 5.5, 5.9, 5.11-5.19 * text/html 2012-11-20T03:32:37+00:00 allison (allison@undisclosed.example.com) Laboratory https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/laboratory?rev=1353382357&do=diff Laboratory See here for important policies on laboratory requirements, submission and evaluation The laboratory is hands on and students should have experience with electronic circuits and computer organization and digital logic (e.g. strongly recommended or prerequisite courses are Phys 3150 and CSE 2021). Some useful information and examples for the DE2 board are availble from text/html 2012-10-22T21:01:37+00:00 allison (allison@undisclosed.example.com) tut_signaltapii_verilogde2.pdf https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/?image=tut_signaltapii_verilogde2.pdf&ns=0&rev=1350939697&tab_details=history&media_do=diff&do=media <img src="https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/lib/images/fileicons/svg/pdf.svg" alt="tut_signaltapii_verilogde2.pdf" loading="lazy" width="500" height="500" /> text/html 2012-10-15T00:16:57+00:00 allison (allison@undisclosed.example.com) tutorial_quartusii_timing_simulation_verilog.pdf https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/?image=tutorial_quartusii_timing_simulation_verilog.pdf&ns=0&rev=1350260217&tab_details=history&media_do=diff&do=media <img src="https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/lib/images/fileicons/svg/pdf.svg" alt="tutorial_quartusii_timing_simulation_verilog.pdf" loading="lazy" width="500" height="500" />