CSE3201

Contact

Anonymous (anonymous@undisclosed.example.com) — 2012-09-14T18:33:29+00:00

Contact Course Director * Robert Allison * Office: LAS 3051 (Lassonde Building) * Phone: (416) 736-2100 x. 20192 * Email: allison AT cse DOT yorku DOT ca Teaching Assistants * Jianhui Chen, Andrew Speers, Navid Mohaghegh. * Email: {jianhui, speers, navid} AT cse DOT yorku DOT ca

Course Outline

Anonymous (anonymous@undisclosed.example.com) — 2012-09-17T02:32:28+00:00

Course Outline CSE 3201 Fall 2012 Department of Computer Science and Engineering York University, Toronto, Ontario Fall/Winter 2012-2013 Schedule Contact Instructor: R. Allison; TA: Andrew Speers, Jianhui Chen, Navid Mohaghegh Overview In this course we will cover a series of topics in Digital Logic Design including digital circuit families, Boolean Algebra, minimization, combinational circuits, sequential circuits, registers, counters and memory and register transfer level design. The c…

Frequently Asked Questions

Anonymous (anonymous@undisclosed.example.com) — 2007-08-01T14:34:50+00:00

Frequently Asked Questions Here, you can list frequently asked questions from your students along with responses. General Do I need to register for a CSE Computer Account? Yes. Do I need to attend class? If you wish to pass. Tests Do I need to write all tests?

Forums

Anonymous (anonymous@undisclosed.example.com) — 2007-08-02T17:22:57+00:00

Forums This page acts as a future placeholder for a link to a forum system.

Grades

Anonymous (anonymous@undisclosed.example.com) — 2012-09-02T13:42:59+00:00

Grades The weight distribution of the course components is as follows: * 20% - Labs * 15% - Test 1 * 15% - Test 2 * 50% - Final Exam You can view your marks here. Conversion from numeric to letter grade is applied to the overall mark only and in accordance with the following departmental standard:

Important Dates

Anonymous (anonymous@undisclosed.example.com) — 2012-09-02T13:14:38+00:00

Important Dates * Nov 9, 2012 Last date to drop without receiving a grade (unofficial verify with Registrar's office) * Week of October 15 First test * Week of Nov 12 Second test

Laboratory

Anonymous (anonymous@undisclosed.example.com) — 2012-11-20T03:32:37+00:00

Laboratory See here for important policies on laboratory requirements, submission and evaluation The laboratory is hands on and students should have experience with electronic circuits and computer organization and digital logic (e.g. strongly recommended or prerequisite courses are Phys 3150 and CSE 2021). Some useful information and examples for the DE2 board are availble from

Anonymous (anonymous@undisclosed.example.com) — 2012-09-14T01:26:10+00:00

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Policies

Anonymous (anonymous@undisclosed.example.com) — 2012-09-02T14:31:49+00:00

Policies Here, you can list specific course policies. Laboratory Policy A mandatory hardware laboratory component is required for CSE3201 (this is why the course has 4 credit weighting). The laboratory is weekly and requires attendance during the student's lab session. If you cannot attend your lab session you will not be able to continue in the course. Students will work in pairs.

Resources

Anonymous (anonymous@undisclosed.example.com) — 2012-09-18T00:51:06+00:00

Resources Use this page to list additional Resources that may be helpful to your students. * Department of CSE Home Page * York Exam Schedule Other useful reading material * Digital Design, Mano and Ciletti 4th edition Prentice Hall * Digital Design: Principles and Practices, Wakerly, Prentice Hall

Anonymous (anonymous@undisclosed.example.com) — 2024-03-08T14:02:31+00:00

* What's New * Course Outline * Important Dates * Grades * Assignments * Forums * Contact * Policies * Resources * Laboratory * Textbook * FAQs * Academic Dishonesty

Digital Logic Design

Anonymous (anonymous@undisclosed.example.com) — 2012-09-01T13:08:53+00:00

Digital Logic Design Description SC/CSE 3201 4.00 Digital Logic Design Theory and design of logic circuits used in digital systems. This is an intermediate level course that uses a Hardware Design Language to illustrate modern design techniques and is supplemented by hardware laboratory exercise (two hours per week). Prerequisites: A cumulative grade point average of 4.5 or better over all completed major computer science courses; SC/

Textbook

Anonymous (anonymous@undisclosed.example.com) — 2012-09-05T01:41:24+00:00

Textbook You will require the following textbook for this course: * Fundamentals of Digital Logic with Verilog Design, 2/e by Stephen Brown and Zvonko Vranesic, McGraw-Hill, 2008 You may purchase this book through the York University Bookstore.

What's New?

Anonymous (anonymous@undisclosed.example.com) — 2012-10-02T19:39:23+00:00

What's New? Oct 2, 2012 Tests will be held on Oct 17 and November 14. Details to follow. Oct 2, 2012 No TA office hours this week since we have Thanksgiving so no lab on Monday. Office hours resume Oct 12. Sept 22, 2012 Correction to lab 2. Sept 14, 2012