course_outline
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course_outline [2012/10/05 16:07] – jonathan | course_outline [2012/11/28 19:55] (current) – jonathan | ||
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state machine, traces, trace specifications. | state machine, traces, trace specifications. | ||
- | Required: Watch a [[http:// | + | Required: Watch a [[http:// |
===== UML for Requirements ===== | ===== UML for Requirements ===== | ||
- | The suggested text discusses how UML models are used in requirements engineering. We discuss use cases/ | + | The suggested text discusses how UML models are used in requirements engineering. We discuss use cases/ |
+ | |||
+ | ===== Writing requirements for reactive/ | ||
+ | * Difference between transformational and reactive systems | ||
+ | * Safety critical systems are usually reactive | ||
+ | * Difference between proof systems and model checking | ||
+ | * Timed Transition Models | ||
+ | * types, constants and variables | ||
+ | * module templates with in, out and share variables | ||
+ | * module instants | ||
+ | * module compositions | ||
+ | * model-checking and reachability graphs | ||
+ | * temporal logic specifications | ||
+ | * safety properties and liveness properties | ||
+ | * discussion of the the bridge controller | ||
+ | |||
+ | ===== General Considerations ===== | ||
+ | |||
+ | This is covered in the slides in the SVN: Readings/ |
course_outline.1349453249.txt.gz · Last modified: 2012/10/05 16:07 by jonathan