assignments:a2
Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
assignments:a2 [2013/10/08 02:45] – magiero | assignments:a2 [2013/10/08 03:15] (current) – magiero | ||
---|---|---|---|
Line 3: | Line 3: | ||
Due Wed. Oct. 16 at end of class. | Due Wed. Oct. 16 at end of class. | ||
- | Hand in Questions: | + | Hand in Questions: |
- | - **2.39 state the cost for both SOP and POS (assume true and false of inputs | + | - **2.39 state the cost for both SOP and POS (assume true and false of input variables |
- | - | + | - 2.45* |
+ | - 2.48* | ||
+ | - **2.49** | ||
+ | - **Show the transistor-level CMOS circuit schematic (NOT the gate schematic) implementing a 3-input AND gate (AND3).** | ||
+ | - 2.53 | ||
+ | - 2.54* | ||
+ | - 2.55 | ||
+ | - 2.56* | ||
+ | - **2.57** | ||
+ | - Write valid Verilog code for an 8:1 multiplexer " | ||
+ | - 2.69 | ||
+ | - 2.74 | ||
+ | - 3.1* | ||
+ | - 3.2* | ||
+ | - 3.3* | ||
+ | - 3.4* | ||
+ | - **3.5** | ||
+ | - 3.11* | ||
+ | - 3.13* | ||
+ | - **3.14** |
assignments/a2.1381200343.txt.gz · Last modified: 2013/10/08 02:45 by magiero