https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/ 2026-05-11T16:55:26+00:00 https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/ https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/_media/wiki:dokuwiki-128.png text/html 2013-10-02T16:57:07+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/contact?rev=1380733027&do=diff Contact Course Director * Sebastian Magierowski (Lassonde Building) * office: LAS 1012B * phone: (416) 736-2100 x. 44652 * email: magiero AT cse DOT yorku DOT ca * office hours: WF 11am-noon Teaching Assistants * Syed Zahidul Islam * text/html 2013-09-17T19:44:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/course_outline?rev=1379447076&do=diff Course Outline Staff Instructor: Sebastian Magierowski Teaching Assistants: Syed Zahidul Islam, Giancarlo Ayala-Charca Overview In this course we will cover a series of topics in Digital Logic Design including digital circuit families, Boolean Algebra, minimization, combinational circuits, sequential circuits, registers, counters and memory and register transfer level design. The course and the labs will use Verilog to describe and design circuits. text/html 2007-08-01T14:34:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/faq?rev=1185978890&do=diff Frequently Asked Questions Here, you can list frequently asked questions from your students along with responses. General Do I need to register for a CSE Computer Account? Yes. Do I need to attend class? If you wish to pass. Tests Do I need to write all tests? text/html 2007-08-02T17:22:57+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/forums?rev=1186075377&do=diff Forums This page acts as a future placeholder for a link to a forum system. text/html 2013-09-09T15:30:28+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/grades?rev=1378740628&do=diff Grades The weight distribution of the course components is as follows: * 15% - Labs * 10% - Assignments (only the best 3 out of 4 assignments will be used for the final mark) * 25% - Midterm * 50% - Final Exam You can view your marks on Moodle text/html 2013-10-02T16:58:07+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/important_dates?rev=1380733087&do=diff Important Dates Midterm Wednesday October 23, 2013. In class Assignments Assig. 1 Due: Wed. Sept. 25 (at end of class) Assig. 2 Due: Wed. Oct. 16 (at end of class) Assig. 3 Due: Wed. Nov. 13 (at end of class) Assig. 4 Due: Wed. Dec. 04 (at end of class) text/html 2013-11-07T17:34:44+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/labs?rev=1383845684&do=diff Labs Lab 9: A Finite State Machine Lab Date: Mon. Nov. 25, 2013, in LAS 1004A (our last lab) Implement a traffic light control system. Lots of detail to account for here so read carefully and start thinking ahead. [ Lab 9] Lab 8: Counters & Registers text/html 2007-07-31T18:55:53+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/policies?rev=1185908153&do=diff Policies Here, you can list specific course policies. Academic Dishonesty For more information on Academic Dishonesty, click here. text/html 2007-07-31T18:59:29+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/resources?rev=1185908369&do=diff Resources Use this page to list additional Resources that may be helpful to your students. * Department of CSE Home Page * York Exam Schedule text/html 2024-03-08T14:02:31+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/sidebar?rev=1709906551&do=diff * What's New * Course Outline * Important Dates * Grades * Labs * Assignments * Assignment 1 * Assignment 2 * Assignment 3 * Assignment 4 * Contact * Policies * Resources * Textbook * FAQs * Academic Dishonesty text/html 2013-09-09T14:49:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/start?rev=1378738186&do=diff SC/CSE 3201 DIGITAL LOGIC DESIGN Description LE/CSE 3201 4.00 Digital Logic Design Theory and design of logic circuits used in digital systems. This is an intermediate level course that uses a Hardware Design Language to illustrate modern design techniques and is supplemented by hardware laboratory exercise (two hours per week). Prerequisites: A cumulative grade point average of 4.5 or better over all completed major computer science courses; SC/ text/html 2013-09-09T15:53:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/textbook?rev=1378741999&do=diff Textbook You will require the following textbook for this course: * Fundamentals of Digital Logic with Verilog Design, 3/e by Stephen Brown and Zvonko Vranesic, McGraw-Hill, 2014 You may purchase this book through the York University Bookstore. text/html 2013-12-11T03:08:00+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2013-14/F/3201/whats_new?rev=1386731280&do=diff What's New? Here, you can list what's new in your course. Dec. 10, 2013 Assig. 4 Solutions posted at the bottom of the Wiki Assignment 4 page (not on Moodle). Sorry for the delay, I couldn't seem to upload on anything for the past couple of days, until I tried it with the firefox browser.