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labs [2013/09/18 20:06] – magierolabs [2013/11/07 17:34] (current) – magiero
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 ====== Labs ====== ====== Labs ======
 +
 +==== Lab 9: A Finite State Machine ====
 +
 +__Lab Date: Mon. Nov. 25, 2013, in LAS 1004A (our last lab)__
 +
 +Implement a traffic light control system.  Lots of detail to account for here so read carefully and start thinking ahead.
 +
 +{{lab9.pdf | Lab 9}}
 +
 +==== Lab 8: Counters & Registers ====
 +
 +__Lab Date: Mon. Nov. 18, 2013, in LAS 1004A__
 +
 +Implement a variety of counters as well as a linear feedback shift register (LFSR).
 +
 +{{lab8.pdf | Lab 8}}
 +
 +==== Lab 7: Latches and Flip-Flops ====
 +
 +__Lab Date: Mon. Nov. 11, 2013, in LAS 1004A__
 +
 +Implement latches and flip-flops in an FPGA.  Use them as storage elements in the assignment of numbers to a 7-segment display.
 +
 +{{lab7.pdf | Lab 7}}
 +
 +==== Lab 6: Timing Measurements ====
 +
 +__Lab Date: Mon. Nov. 4, 2013 in LAS 1004A__
 +
 +Create test vectors for your multiplier (from Lab 5) and verify its operation more thoroughly using Altera's system-level debugging tool, SignalTap.  Links on Altera timing and SignalTap below (recommended to go over these before Lab 6).
 +
 +{{lab6.pdf | Lab 6}}
 +
 +{{timingsimulation.pdf | Timing Simulations}}
 +
 +{{signaltap.pdf | Signal Tap}}
 +
 +==== Lab 5: Multipliers ====
 +
 +__Lab Date: Mon. Oct. 28, 2013 in LAS 1004A__
 +
 +Implement multipliers using a couple different adder arrangements.
 +
 +{{lab5.pdf | Lab 5}}
 +
 +==== Lab 4: Number Systems ====
 +
 +__Lab Date: Mon. Oct. 21, 2013 in LAS 1004A__
 +
 +Displaying BCD numbers and adding them up.
 +
 +{{lab4.pdf | Lab 4}} 
 +
 +==== Lab 3: Seven Segment Displays ====
 +
 +__Lab Date: Mon. Oct. 7, 2013 in LAS 1004A__
 +
 +Writing Verilog code to control the seven-segment display on your DE2.
 +
 +{{lab3.pdf | Lab 3}}
 +
 +==== Lab 2: Boolean Logic and Digital Circuits ====
 +
 +__Lab Date: Mon. Sept. 30, 2013 in LAS 1004A__
 +
 +Writing a variety of Verilog modules for the DE2 implementing a parity function as well as a parity checker.  **Make sure to do your prelab** (see Lab 2 description below).
 +
 +{{lab2.pdf | Lab 2}}
  
 ==== Lab 1: Verilog/Schematic Design Entry Tutorial ===== ==== Lab 1: Verilog/Schematic Design Entry Tutorial =====
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 {{DE2_pin_assignments.txt | DE2 Pin Assignment File}} {{DE2_pin_assignments.txt | DE2 Pin Assignment File}}
 +
 +{{de2_pin_table.pdf | DE2 Pin Table}} (just the file above, but in table format)
  
 ===== Verilog Resources ===== ===== Verilog Resources =====
labs.1379534791.txt.gz · Last modified: by magiero