===== Expected Learning Outcomes =====

By the end of the course, you are expected to be able to:

  * Translate a given high-level program to assembly/machine language
    * Represent numbers, characters, and other forms of data in binary
    * Express logic using assembly language instructions
    * Utilize registers, the stack, the heap, and the data segment to store data
    * Encode assembly language instructions in machine language format 
    
  * Build a CPU out of basic building blocks such as gates and flip-flops
    * Build the ALU using gates and Verilog
    * Design the CPU's datapath and control
    * Implement a pipeline and handle its hazards
    * Augment the CPU with a cache

  * Assess the end-to-end performance
    * Identify the key performance drivers and their physical limits
    * Compare and contrast the RISC and CISC approaches
    * Compute the throughput of a pipelined CPU for a given code fragment
    * Analyze the effect of a cache of a given specs on the system's performance