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--- format [2010/12/29 22:11] – roumani
+++ format [2011/01/25 16:19] (current) – roumani
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-====== Format ======
 ===== Expected Learning Outcomes =====
-By the end of the course, the students is expected to be able to:
-  - Translate high-level programs (such as those in Java or C) to assembly language and, finally, in machine language on an instruction-by-instruction basis.
-  - Write and debug simple programs involving input/output routines, arithmetic operations, decisions, repetitions, and procedures directly in an assembly language such as MIPS.
-   - Design a prototype Arithmetic Logic Unit (ALU) from basic building blocks such as gates and flip flops using elementary logic design concepts.
-   - Construct the datapath and control unit of the processor using either of the: (i) single cycle implementation; (ii) multiple cycle implementation, or (iii) pipelining; and explain how computer execute programs in these implementations.
-   - Abstract computer hardware by building modules in a hardware description language such as Verilog.
-===== Activities =====
-  * **Labs**
-The labs focus on technology. They are self-contained and enable you to learn the MIPS assembly and machine languages and explore the CPU datapath and control through Verilog.
-  * **Lectures**
-The lectures focus on concepts, principles, and the big-picture. Certain MIPS-specific details are also covered to demonstrate complex ideas or to compare and contrast implementations.
-  * **Quizzes and Games**
-Some lectures will include pop quizzes or games such as Jeopardy aimed at reviewing and discussing ideas, uncovering fallacies, and avoiding pitfalls. These activities are intended for active-learning, not assessment.
+By the end of the course, you are expected to be able to:
-  * **Assigned Readings**
+  * Translate a given high-level program to assembly/machine language
+    * Represent numbers, characters, and other forms of data in binary
+    * Express logic using assembly language instructions
+    * Utilize registers, the stack, the heap, and the data segment to store data
+    * Encode assembly language instructions in machine language format
+  * Build a CPU out of basic building blocks such as gates and flip-flops
+    * Build the ALU using gates and Verilog
+    * Design the CPU's datapath and control
+    * Implement a pipeline and handle its hazards
+    * Augment the CPU with a cache
-The lecture notes (linked to from the Weekly Schedule) include assigned readings from the textbook and from selected articles. These are integral parts of the learning experience of this course.
+  * Assess the end-to-end performance
+    * Identify the key performance drivers and their physical limits
+    * Compare and contrast the RISC and CISC approaches
+    * Compute the throughput of a pipelined CPU for a given code fragment
+    * Analyze the effect of a cache of a given specs on the system's performance
-  * **Forum**
-You are strongly encouraged to contribute to this group. By simply framing an issue into a question, you help sharpen the learning focus for yourself and for others. And by answering a question or engaging in a discussion, you sharpen your ability to prove a point or assess one.