pipelines
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pipelines [2007/11/23 16:11] – roumani | pipelines [2007/11/23 20:45] (current) – roumani | ||
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====== Pipelining ====== | ====== Pipelining ====== | ||
- | This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU //not// by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is also //not/ minimized but it is offset by high throughput. Stage balancing, pipeline structure, and hazard detection and avoidance are the key drivers of pipelining. | + | This lecture covers the design and implementation of the MIPS CPU using a pipeline. This implementation addresses the two main faults of the single-cycle CPU //not// by eliminating hardware redundancy but by allowing more than one instruction to execute at the same time thereby no hardware unit will be idle. The high latency of the single-cycle approach is also //not// minimized but it is offset by high throughput. Stage balancing, pipeline structure, and hazard detection and avoidance are the key drivers of pipelining. |
===== Outline ===== | ===== Outline ===== | ||
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* One can increase throughput despite an increase in latency | * One can increase throughput despite an increase in latency | ||
* For a process to be pipelined, the stages must be balanced and no structural violations should be allowed | * For a process to be pipelined, the stages must be balanced and no structural violations should be allowed | ||
- | * Dependencies tend to lower the pipeline' | + | * Dependencies tend to lower the pipeline' |
===== Slides from Lecture ===== | ===== Slides from Lecture ===== | ||
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* Read Sections 6.1 through 6.7 of the textbook. | * Read Sections 6.1 through 6.7 of the textbook. | ||
- | * Do the multi-cycle | + | * Do the pipeline |
pipelines.1195834265.txt.gz · Last modified: 2007/11/23 16:11 by roumani