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verilog_modules [2007/11/16 01:17] – roumaniverilog_modules [2007/11/16 01:29] (current) – roumani
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 So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves.  So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. 
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 ===== Outline ===== ===== Outline =====
  
-  * Performing PC+4 using the main ALU +A Verilog top-level (i.e. ''main'') module consists of the following section: 
-  * Performing PC+4 + 4*Label using the main ALU + 
-  * Adding registers to hold intermediate data +  * A ''module'' header 
-  * Combining the two memory units +  * A //declaration// block 
-  * Issuing the control signals for State #0 +  * A //circuit// block where all the needed components are instantiated and connected via ''assign''. 
-  * Doing something useful in State #1 +  * One ''initial'' block 
-  * Instruction-dependent states+  * One or more ''always'' blocks. 
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 +A Verilog component (i.e. reusable in other modules) differs slightly from a top-level module as indicated below: 
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 +  * The ''module'' headers is followed by //ports//, the names of the wires that connect this component to the outside world. 
 +  * The declaration section indicates which wire is incoming (by using ''input'') and which is outgoing (using ''output''). 
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 +The functionality of the component can be implemented procedurally (in an ''always'' block) or structurally (in the circuit instantiation section).   
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 ===== To Do ===== ===== To Do =====
  
-   * Look at the program ''alu1b'' and its tester ''alu1bClient'' in the //Resource Directory//. ''alu1b' is a 1-bit adder component made up of basic gates.+  * Look at the program ''alu1b'' and its tester ''alu1bClient'' in the //Resource Directory//. ''alu1b'' is a 1-bit adder component made up of basic gates. 
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 +  * Look at the program ''alu2b'' and its tester ''alu2bClient'' in the //Resource Directory//. ''alu2b'' is a 2-bit adder component made up of two ''alu1b'' adders.
  
-  * Look at the program ''alu2b'' and its tester ''alu2bClient'' in the //Resource Directory//. ''alu2b' is a 2-bit adder component made up of two ''alu1b'' adders. 
verilog_modules.1195175843.txt.gz · Last modified: 2007/11/16 01:17 by roumani