verilog_modules
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| So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. | So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. | ||
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| ===== Outline ===== | ===== Outline ===== | ||
| - | * Performing PC+4 using the main ALU | + | A Verilog top-level (i.e. '' |
| - | * Performing PC+4 + 4*Label using the main ALU | + | |
| - | * Adding registers to hold intermediate data | + | |
| - | * Combining the two memory units | + | |
| - | * Issuing the control signals for State #0 | + | |
| - | * Doing something useful in State #1 | + | |
| - | * Instruction-dependent states | + | |
| + | * A '' | ||
| + | * A // | ||
| + | * A //circuit// block where all the needed components are instantiated and connected via '' | ||
| + | * One '' | ||
| + | * One or more '' | ||
| + | A Verilog component (i.e. reusable in other modules) differs slightly from a top-level module as indicated below: | ||
| + | * The '' | ||
| + | * The declaration section indicates which wire is incoming (by using '' | ||
| + | The functionality of the component can be implemented procedurally (in an '' | ||
| - | ===== To Do ===== | ||
| - | * Look at the program '' | ||
| - | '' | ||
| - | * Unordered List Item | ||
| - | | ||
| - | | + | ===== To Do ===== |
| + | |||
| + | * Look at the program '' | ||
| + | |||
| + | | ||
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