CSE2021

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====== Verilog Modules ======

So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves. 


===== Outline =====

A Verilog top-level (i.e. ''main'') module consists of the following section:

  * A ''module'' header
  * A //declaration// block
  * A //circuit// block where all the needed components are instantiated and connected via ''assign''.
  * One ''initial'' block
  * One or more ''always'' blocks.

A Verilog component (i.e. reusable in other modules) differs slightly from a top-level module as indicated below:

  * The ''module'' headers is followed by //ports//, the names of the wires that connect this component to the outside world.
  * The declaration section indicates which wire is incoming (by using ''input'') and which is outgoing (using ''output'').

The functionality of the component can be implemented procedurally (in an ''always'' block) or structurally (in the circuit instantiation section).  













===== To Do =====

  * Look at the program ''alu1b'' and its tester ''alu1bClient'' in the //Resource Directory//. ''alu1b'' is a 1-bit adder component made up of basic gates.

  * Look at the program ''alu2b'' and its tester ''alu2bClient'' in the //Resource Directory//. ''alu2b'' is a 2-bit adder component made up of two ''alu1b'' adders.