2 lab section
The lab material is developed by Prof. Hamzeh Roumani
The lab manual presents a simple introduction to Verilog. If you are going into computer engineering or electrical engineering, Verilog is very important. here are some more resources that will help you understand verilog
A very good tutorial by Dr. Dr. Daniel C. Hyde Computer Science Department Bucknell University Introduction
Guidlines Voted Best Paper SNUG-2000 San Jose, CA
veriwell (verilog simulator) veriwell.pdf Author unknown
* MIPS project – this is a 2 weeks lab here is an example input filetest_case.txt and the output response.txt
The above files contains addi and or which you were asked to implelemnt, here is the new input file code_1.txt, the output file response_1.txt and the asm file case.txt – Note that the out file example does not include the separator “=====” after displaying the register contents, your code should
How to submit: first do man submit. C files should be submitted to a1c and java files to a1j. C file MUST be named ProjectMips.c and the main class in java MUST be called ProjectMips.java. The deadline is Tuesday Nov 4 midnight
I have been asked by many students on when the report is due, This is a 2 lab sessions project, meaning in the second lab session (either oct. 14 or Oct 20, dedpending on your section), you should complete the project (no demo though). Then at the beginning of the following lab (Oct 21, or Oct 27) you submit the report