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--- course_outline [2014/12/01 21:07] – aboelaze
+++ course_outline [2015/01/07 19:51] (current) – aboelaze
@@ Line 9: / Line 9: @@
 {{:week_1.pdf|Introduction}}
-{{:week_1.pdf|Verilog tutorial}} A very good Introduction to Verilog by Prof. Hyde Bucknell University. it is rather old (1997) but very good introduction to Verilog
+a good verilog paper {{:verilog_coding_style_guidelines.pdf|}}
+{{:verilog.pdf|}}} A very good Introduction to Verilog by Prof. Hyde Bucknell University. it is rather old (1997) but very good introduction to Verilog
 ----
@@ Line 127: / Line 129: @@
 Pipelines {{:processor_part_3.pdf|Implementation}}
-**Quiz 3** is on Wednesday
+**Quiz 3** is on Wednesday, and the solution is here {{:quiz_3_sol.pdf|}}
 Cache
 Check your marks fro assignments and quizzes. {{:post_2021026.pdf|marks}}
+Labs A to K marks {{:labs_a_k_posted.pdf|}} if you submitted your lab late, it is not in this file
 few of you submitted quiz 2 with no name on it, obviously no mark is given.
@@ Line 146: / Line 151: @@
 ==== Final Exam ====
+Final **NON OFFICIAL ** letter grades   {{:letter_grade_1.pdf|}}  and  {{:letter_grade_2.pdf|}}