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course_outline [2014/12/12 22:10] – aboelazecourse_outline [2015/01/07 19:51] (current) – aboelaze
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 a good verilog paper {{:verilog_coding_style_guidelines.pdf|}} a good verilog paper {{:verilog_coding_style_guidelines.pdf|}}
  
-{{:week_1.pdf|Verilog tutorial}} A very good Introduction to Verilog by Prof. Hyde Bucknell University. it is rather old (1997) but very good introduction to Verilog+{{:verilog.pdf|}}} A very good Introduction to Verilog by Prof. Hyde Bucknell University. it is rather old (1997) but very good introduction to Verilog
  
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 Check your marks fro assignments and quizzes. {{:post_2021026.pdf|marks}} Check your marks fro assignments and quizzes. {{:post_2021026.pdf|marks}}
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 +Labs A to K marks {{:labs_a_k_posted.pdf|}} if you submitted your lab late, it is not in this file
  
 few of you submitted quiz 2 with no name on it, obviously no mark is given. few of you submitted quiz 2 with no name on it, obviously no mark is given.
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 ==== Final Exam ==== ==== Final Exam ====
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 +Final **NON OFFICIAL ** letter grades   {{:letter_grade_1.pdf|}}  and  {{:letter_grade_2.pdf|}}
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