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--- lab [2014/09/29 20:18] – aboelaze
+++ lab [2014/10/31 21:02] (current) – aboelaze
@@ Line 20: / Line 20: @@
 San Jose, CA
-veriwell (verilog simulator) {{:veriwell.pdf|}}
+veriwell (verilog simulator) {{:veriwell.pdf|}} Author unknown
+ * {{:project_1.pdf|MIPS project}} -- this is a 2 weeks lab <del>here is an example input file{{:test_case.txt|}} and the output {{:response.txt|}}</del>
+The above files contains addi and or which you were asked to implelemnt, here is the new input file {{:code_1.txt|}}, the output file {{:response_1.txt|}} and the asm file {{:case.txt|}} -- Note that the out file example does not include the separator "=====" after displaying the register contents, your code should
+**How to submit**: first do man submit. C files should be submitted to a1c and java files to a1j. C file **MUST** be named ProjectMips.c and the main class in java **MUST** be called ProjectMips.java. **The deadline is Tuesday Nov 4  midnight**
+<fc red> I have been asked by many students on when the report is due,
+This is a 2 lab sessions project, meaning in the second lab session (either oct. 14 or Oct 20, dedpending on your section), you should complete the project (no demo though). Then at the beginning of the following lab (Oct 21, or Oct 27) you submit the report </fc>
+  * {{:labk.pdf|Lab K}}
+  * {{:labl.pdf|Lab L}}
+  * {{:labm.pdf|Lab M}}
+  *{{:labn.pdf|Lab N}}