====== Course Outline ======

The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:

===== Lecture 1 =====

{{:eecs3201_dig_l1.pdf|Introduction}}

===== Lecture 2 =====

{{:eecs3201_dig_l2.pdf|Basic Concepts + Review of Numbering Systems}}

===== Lecture 3 =====

{{:eecs3201_dig_l3.pdf|Logic Gates and Basic Logic Circuits}}

===== Lecture 4 =====

{{:eecs3201_dig_l4.pdf|Introduction to Verilog HDL}}

===== Lecture 5 =====

{{:eecs3201_dig_l5.pdf|Boolean Algebra}}

===== Lecture 6 =====

{{:eecs3201_dig_l6.pdf|Karnaugh Maps and Basic Arithmetic Circuits}}

===== Lecture 7 =====

{{:eecs3201_dig_l7.pdf|Multipliers, Multiplexers, Decoders, and RAM}}

===== Lecture 8 =====

{{:eecs3201_dig_l8.pdf|ROMs, PLDs, and ALUs}}

===== Lecture 9 =====

{{:eecs3201_dig_l9.pdf|Introduction to Sequential Circuits}}

===== Lecture 10 =====

{{:eecs3201_dig_l10.pdf|Analysis of Sequential Circuits}}

===== Lecture 11 =====

{{:eecs3201_dig_l11.pdf|Design of Sequential Circuits + Guidelines for Midterm}}

===== Midterm =====

===== Lecture 12 =====

{{:eecs3201_dig_l12.pdf|Registers and Counters}}

===== Lecture 13 =====

{{:eecs3201_dig_l13.pdf|Synthesis-Friendly Verilog}}


===== Lecture 14 =====

{{:eecs3201_dig_l14.pdf|Modular Design + ASM's}}


===== Lecture 15 =====

{{:eecs3201_dig_l15.pdf|Design with MUX's}}


===== Lecture 16 =====

{{:eecs3201_dig_l16.pdf|Pipelining}}


===== Lecture 17 =====

{{:eecs3201_dig_l17.pdf|Fast Adders I}}


===== Lecture 18 =====


{{:eecs3201_dig_l18.pdf|Fast Adders II}}


===== Guidelines for Final Exam =====

{{:eecs3201_guidelines_final_exam_2.pdf|Read this well while studying for final exam}}

===== Final Exam =====