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--- course_outline [2014/10/02 00:09] – iamer
+++ course_outline [2014/12/11 03:32] (current) – iamer
@@ Line 26: / Line 26: @@
 {{:eecs3201_dig_l6.pdf|Karnaugh Maps and Basic Arithmetic Circuits}}
+===== Lecture 7 =====
+{{:eecs3201_dig_l7.pdf|Multipliers, Multiplexers, Decoders, and RAM}}
+===== Lecture 8 =====
+{{:eecs3201_dig_l8.pdf|ROMs, PLDs, and ALUs}}
+===== Lecture 9 =====
+{{:eecs3201_dig_l9.pdf|Introduction to Sequential Circuits}}
+===== Lecture 10 =====
+{{:eecs3201_dig_l10.pdf|Analysis of Sequential Circuits}}
+===== Lecture 11 =====
+{{:eecs3201_dig_l11.pdf|Design of Sequential Circuits + Guidelines for Midterm}}
 ===== Midterm =====
-===== Drop Deadline =====
+===== Lecture 12 =====
+{{:eecs3201_dig_l12.pdf|Registers and Counters}}
 ===== Lecture 13 =====
-===== Final Exam =====
+{{:eecs3201_dig_l13.pdf|Synthesis-Friendly Verilog}}
+===== Lecture 14 =====
+{{:eecs3201_dig_l14.pdf|Modular Design + ASM's}}
+===== Lecture 15 =====
+{{:eecs3201_dig_l15.pdf|Design with MUX's}}
+===== Lecture 16 =====
+{{:eecs3201_dig_l16.pdf|Pipelining}}
+===== Lecture 17 =====
+{{:eecs3201_dig_l17.pdf|Fast Adders I}}
+===== Lecture 18 =====
+{{:eecs3201_dig_l18.pdf|Fast Adders II}}
+===== Guidelines for Final Exam =====
+{{:eecs3201_guidelines_final_exam_2.pdf|Read this well while studying for final exam}}
+===== Final Exam =====