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--- course_outline [2014/11/05 21:38] – iamer
+++ course_outline [2014/12/11 03:32] (current) – iamer
@@ Line 53: / Line 53: @@
 {{:eecs3201_dig_l12.pdf|Registers and Counters}}
-===== Final Exam =====
+===== Lecture 13 =====
+{{:eecs3201_dig_l13.pdf|Synthesis-Friendly Verilog}}
+===== Lecture 14 =====
+{{:eecs3201_dig_l14.pdf|Modular Design + ASM's}}
+===== Lecture 15 =====
+{{:eecs3201_dig_l15.pdf|Design with MUX's}}
+===== Lecture 16 =====
+{{:eecs3201_dig_l16.pdf|Pipelining}}
+===== Lecture 17 =====
+{{:eecs3201_dig_l17.pdf|Fast Adders I}}
+===== Lecture 18 =====
+{{:eecs3201_dig_l18.pdf|Fast Adders II}}
+===== Guidelines for Final Exam =====
+{{:eecs3201_guidelines_final_exam_2.pdf|Read this well while studying for final exam}}
+===== Final Exam =====