EECS2021

Lab 1 Data representation

lab 2 Introduction to Assembly

There is an excellent spim tutorial at the University of Washington SPIM tutorial

lab 3 Translating Utility Classes

The lab demo will be limited to C1 to C6 only, C7 and C8 could be demoed the following lab.

project details here

here is one example of an input file input_project.txt and here is some explanation explanation.pdf

The simulator output is the contents of the 32 register. The format is four values per line. The register number is between 2 square brackets, followed by the actual value [0]0 [1]12 [2]0 [3]24 [4]12 and so on

The output could be in decimal or hex, if hex include 0x before the number. The output should be formatted to align the registers vertically, [5] should be right under [1]

The project is due midnight Nov. 2

Submit the file as Project.java (or Project.c)

The name of the file that include the

Here is an example input

The output should be

Lab k Introduction to Verilog

Note that The Monday section will work on the project