Differences

This shows you the differences between two versions of the page.

--- course_outline [2015/11/06 16:57] – aboelaze
+++ course_outline [2015/12/08 19:18] (current) – aboelaze
@@ Line 56: / Line 56: @@
 Dynamic scheduling {{:caqa5e_ch3_rob.pdf|Tomasulo and ROB}} and here {{:caqa5e_ch3_rob_2slides.pdf|2 slides per page}} section 3.6
 <fc red> ** Quiz 1 (Thursday)** </fc>
 ----
@@ Line 97: / Line 97: @@
 Here is a {{:paper_survey.pdf|list}} of papers for the paper review project. If you have another idea, please discuss it with me.
+====== Midterm marks are posted on ePost ======
 ----
@@ Line 104: / Line 107: @@
 ===== Week 10 Week of Nov. 9=====
-Virtual memory
+Virtual memory  {{:vm.pdf|here}}
 Assignment 2 has been posted
@@ Line 120: / Line 123: @@
 Thread level parallelism and cache coherence (Chapter 5)
+here is an example trace file. the format is **instruction: R/W memory_address**
+{{:test2.txt|Trace}}
 ----
@@ Line 126: / Line 133: @@
 ===== Week 12 Week of Nov. 23=====
-<fc red> ** Quiz 3 (Thursday) ** </fc>
+<fc red> ** Quiz 3 (Thursday) ** </fc> The quiz will cover virtual memory and DRAM. Virtual memory is section 2.4 + class notes. For DRAM, class notes
-Continue with cache coherence
+Cache coherence {{:cache_coherence_1.pdf|Part 1}}
+Examples on  {{:cache_coherence_protocols.pdf|snoopy and directory based protocols}}
@@ Line 138: / Line 147: @@
 NoC Network on Chip, or how to connect the cores
+The final exam will cover these topics
+  * Chapter 1
+  * Cahpter 2  2.1-2.3 and Virtual memory slides
+  * Chapter 3   3.1-3.9, 3.12 and DRAM notes
+  * Chapter 5  5.1-5.6
 ----