https://wiki.eecs.yorku.ca/course_archive/2015-16/F/4201/ 2026-09-16T23:50:09+00:00 https://wiki.eecs.yorku.ca/course_archive/2015-16/F/4201/ https://wiki.eecs.yorku.ca/course_archive/2015-16/F/4201/_media/wiki:dokuwiki-128.png text/html 2015-09-28T15:26:39+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2015-16/F/4201/assignments:a1?rev=1443453999&do=diff Assignment 1 Due Oct 5, 5pm either in person or by email * 1.4 * 1.5 * Consider the following piece of code ADD R1, R2, R3 NOT R4, R2 ADD R3, R1, R3 SUB R3, R3, R4 MUL R1, R4, R3 AND R2, R4, R3 XOR R4, R1, R3 BNE R4, R1, _LABEL Assume unlimited resources, we are only limited by dependence between the instructions. How many cycles I need to runt his code? text/html 2016-01-08T15:30:32+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2015-16/F/4201/assignments:a2?rev=1452267032&do=diff Assignment 2 Write a cache simulator, you may use Java or C. The simulator takes a trace file and produces the miss rate. The trace files consists of multiple lines, each lines three fields instruction: R/W memory address The simulator accepts as command line arguments as follows text/html 2007-08-01T13:58:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2015-16/F/4201/assignments:a3?rev=1185976730&do=diff Assignment 3 text/html 2007-08-08T20:05:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2015-16/F/4201/assignments:start?rev=1186603558&do=diff Assignments Here, you can link to your course assignments: * Assignment 1 * Assignment 2 * Assignment 3