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CSE2021 is a unique course in that it bridges the gap between software (S/W) and hardware (H/W) and exposes the roles played by the operating system (O/S) and the digital logic (D/L) circuits. It relies on a hierarchy of abstractions to present the material in layers, switching roles from “using” to “implementing” at every stage. It follows the journey of instructions from high-level to assembly and machine code, through the stack, the heap, and the caches, to the CPU's datapath and control. The lecture coverage is augmented by labs that provide hands-on experience in MIPS and Verilog. | CSE2021 is a unique course in that it bridges the gap between software (S/W) and hardware (H/W) and exposes the roles played by the operating system (O/S) and the digital logic (D/L) circuits. It relies on a hierarchy of abstractions to present the material in layers, switching roles from “using” to “implementing” at every stage. It follows the journey of instructions from high-level to assembly and machine code, through the stack, the heap, and the caches, to the CPU's datapath and control. The lecture coverage is augmented by labs that provide hands-on experience in MIPS and Verilog. | ||
- | ===== Lecture Times ===== | + | ===== Expected Learning Outcomes |
- | * Section A: Mondays and Fridays, 11:00am - 12:00pm, CSE 111 | + | By the end of the course, you are expected to be able to: |
+ | * Translate a given high-level program to assembly/ | ||
+ | * Represent numbers, characters, and other forms of data in binary | ||
+ | * Express logic using assembly language instructions | ||
+ | * Utilize registers, the stack, the heap, and the data segment to store data | ||
+ | * Encode assembly language instructions in machine language format | ||
+ | |||
+ | * Build a CPU out of basic building blocks such as gates and flip-flops | ||
+ | * Build the ALU using gates and Verilog | ||
+ | * Design the CPU's datapath and control | ||
+ | * Implement a pipeline and handle its hazards | ||
+ | * Augment the CPU with a cache | ||
+ | |||
+ | * Assess the end-to-end performance | ||
+ | * Identify the key performance drivers and their physical limits | ||
+ | * Compare and contrast the RISC and CISC approaches | ||
+ | * Compute the throughput of a pipelined CPU for a given code fragment | ||
+ | * Analyze the effect of a cache of a given specs on the system' | ||
+ | |||
+ | ===== Instructor & Office Hours ===== | ||
+ | |||
+ | * Instructor: Gulzar Khuwaja | ||
+ | |||
+ | * Lectures: W 7:00-10:00 pm in LSB 105 | ||
+ | * Labs: M 7:00-10:00 pm in LAS 1006 | ||
+ | |||
+ | * Office Hours: W 5:30–6:30 pm in LAS 2015 | ||
+ | * Office Phone: (416) 736-2100 x 70139 (available only during office hours) | ||
+ | |||
+ | * Email: khuwaja@cse.yorku.ca | ||
+ | * Email Filter: The string CSE2021/X in the Subject field, where X is your username on red@cse | ||
+ | |||
+ | ===== Teaching Assistants ===== | ||
+ | |||
+ | * Davoudi, Heidar | ||
+ | * Jia, Meng | ||
+ | * Moury, Sanjida | ||
+ | * Pan, Hengyue | ||
+ | | ||
+ | ^ TIME ^ OFFICE ^ NAME | ||
+ | | Monday 6:00pm - 7:00pm | LAS 3027 | Meng Jia | mjia@cse.yorku.ca | Any question about labs | | ||
+ | |||
+ | ===== Textbooks ===== | ||
+ | |||
+ | **Required** (available in the bookstore and on reserve in Steacie): | ||
+ | * Computer Organization and Design, 5th Edition: The Hardware/ | ||
+ | |||
+ | **References**: | ||
+ | * MIPS Assembly Language Programming, | ||
+ | * Structured Computer Organization, | ||
+ | * MIPS RISC Architecture, | ||
+ | * Computer Organization, |
start.1461460464.txt.gz · Last modified: 2016/04/24 01:14 by khuwaja