====== Course Outline ======

The course outline is a guideline to topics that will be discussed in the course, and when they will be discussed:

===== Week 1 (Tuesday 8, 2016) =====

{{:week_1.pdf|Introduction}} trends in technology

Reading: Textbook: 1.1-1.4

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===== Week 2 (Week of 9/12/2016) =====
Fundamentals of quantitative design and analysis  {{:chapter_1_week_2.pdf|Part 2}} Trends in cost, dependability and perfromance

**Reading**: Textbook 1.5-1.9

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===== Week 3 (MWeek of 9/19/2016) =====


{{:cache_1-organization.pdf|Cache Organization}} Chapter 2.1

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===== Week 4 (Week of 9/26/2016) =====

cache {{:chapter_2_cache_performance.pdf|Performance}}

===== Week 5 -- Week of Oct 3=====

{{:caqa5e_ch2_dram_vm.pdf|DRAM and VM}}

Chapter 3 Instruction level parallelism

{{:caqa5e_ch3_part_a.pdf|MIPS pipeline review}}

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===== Week 6 -- Week of Oct 10=====

Loop unrolling and software pipelining {{:caqa5e_ch3_unrolling.pdf|here}}

<fc red> **Quiz 1 (Thursday)** </fc> Quiz 1 covers up to DRAM + Cache

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===== Week 7 -- Week of Oct 17=====

{{:caqa5e_ch3_prediction.pdf|Prediction}}
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===== Week 8 -- Week of Oct 24=====

Dynamic Scheduling {{:caqa5e_ch3_tomasulo.pdf|Tomasulo's and ROB}}

{{:slides.pdf|}}
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===== Week 9 -- Week of Oct 31=====

<fc red> **Midterm(Tuesday)** </fc>

here is last year {{:midterm_4201_2015.pdf|midterm}} (doesn't mean that what you should concentrate on)

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===== Week 10 -- Week of Nov 7=====

**Paper review** details are {{:paper_survey.pdf|here}}
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===== Week 11 -- Week of Nov 14 =====

<fc red> **Quiz 2 (Thursday)** </fc>  mainly branch predictors

{{:simd.pdf|SIMD}}
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===== Week 12 -- Week of Nov 21 =====

Multithreading and {{:gpu.pdf|GPUs}}

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===== Week 13 -- Week of Nov 28 =====

<fc red> **Quiz 3 (Thursday)**  the quiz will cover SIMD </fc>

{{:interconnection_networks.pdf|Interconnection Networks}}

here is a 50,000 reference {{:trace_50k.txt|trace file}}




===== Final Exam =====

{{:final_4201_15.pdf|Sample final (2015)}}

{{:quiz_3_4201_2016_sol.pdf|Quiz 3 solution}} I was tolerant to what does it means 10 cycles delay (or 6 in case of adder), doe sit means data is rfeady in the 10th or 11th cycle. I accepted both answers