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--- course_outline [2016/10/27 13:45] – aboelaze
+++ course_outline [2016/12/07 16:47] (current) – aboelaze
@@ Line 86: / Line 86: @@
 ===== Week 10 -- Week of Nov 7=====
+**Paper review** details are {{:paper_survey.pdf|here}}
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 ===== Week 11 -- Week of Nov 14 =====
-<fc red> **Quiz 2 (Thursday)** </fc>
+<fc red> **Quiz 2 (Thursday)** </fc>  mainly branch predictors
+{{:simd.pdf|SIMD}}
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@@ Line 98: / Line 101: @@
 ===== Week 12 -- Week of Nov 21 =====
+Multithreading and {{:gpu.pdf|GPUs}}
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 ===== Week 13 -- Week of Nov 28 =====
-<fc red> **Quiz 3 (Thursday)** </fc>
+<fc red> **Quiz 3 (Thursday)**  the quiz will cover SIMD </fc>
+{{:interconnection_networks.pdf|Interconnection Networks}}
+here is a 50,000 reference {{:trace_50k.txt|trace file}}
@@ Line 110: / Line 120: @@
 ===== Final Exam =====
+{{:final_4201_15.pdf|Sample final (2015)}}
+{{:quiz_3_4201_2016_sol.pdf|Quiz 3 solution}} I was tolerant to what does it means 10 cycles delay (or 6 in case of adder), doe sit means data is rfeady in the 10th or 11th cycle. I accepted both answers