https://wiki.eecs.yorku.ca/course_archive/2016-17/F/4201/ 2026-09-08T22:18:23+00:00 https://wiki.eecs.yorku.ca/course_archive/2016-17/F/4201/ https://wiki.eecs.yorku.ca/course_archive/2016-17/F/4201/_media/wiki:dokuwiki-128.png text/html 2016-09-15T19:07:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2016-17/F/4201/assignments:a1?rev=1473966444&do=diff Assignment 1 * 1.1 * 1.4 * 1.11 * 1.13 * 1.14 Due Monday Sept. 26 text/html 2016-11-04T17:22:08+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2016-17/F/4201/assignments:a2?rev=1478280128&do=diff Assignment 2 Write a cache simulator (CacheSim) to simulate a cache. The simulator should be able to simulate up to 64KB cache. The simulator should run as CacheSim size in KB [flags], the flags are shown below The memory is byte addressable with word access, words are 4 bytes text/html 2016-11-10T14:37:05+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2016-17/F/4201/assignments:a3?rev=1478788625&do=diff Assignment 3 Redo the cache Simulator using LRU and pseudo LRU Due last day of classes text/html 2007-08-08T20:05:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.eecs.yorku.ca/course_archive/2016-17/F/4201/assignments:start?rev=1186603558&do=diff Assignments Here, you can link to your course assignments: * Assignment 1 * Assignment 2 * Assignment 3