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start [2017/08/29 17:12] – aboelaze | start [2017/08/29 17:15] (current) – aboelaze | ||
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- Translate | - Translate | ||
- Represent | - Represent | ||
- | - Synthesize hardware of increasing complexity from logic gates to | + | - Synthesize hardware of increasing complexity from logic gates to a simple CPU using a Hardware Description Language. |
- | a simple CPU using a Hardware Description Language. | + | - Evaluate |
- | - Evaluate | + | |
- | different architectures and designs. | + | |
- Describe and critique I/O and Parallel Hardware. | - Describe and critique I/O and Parallel Hardware. | ||
Line 33: | Line 31: | ||
* Section E: Mondays and Wednesdays, 5:30pm - 17:00pm, LAS B | * Section E: Mondays and Wednesdays, 5:30pm - 17:00pm, LAS B | ||
+ | * LAB 01 Mon. 7: | ||
+ | * LAB 02 Tue. 7: | ||
start.1504026729.txt.gz · Last modified: 2017/08/29 17:12 by aboelaze