assignments:a2
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| assignments:a2 [2018/10/03 23:27] – aboelaze | assignments:a2 [2018/10/07 16:31] – aboelaze | ||
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| ====== Assignment 2 ====== | ====== Assignment 2 ====== | ||
| + | **Due date: Oct 16. The midterm is on Oct 18. I will hand out solution after Tuesday | ||
| - What is the number of overhead bits for a 64KB cache with these parameters (tag+dirty+valid)? | - What is the number of overhead bits for a 64KB cache with these parameters (tag+dirty+valid)? | ||
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| - 4-way set associative with 32-word block size | - 4-way set associative with 32-word block size | ||
| - Is it necessary to have the page size be a power of 2? Could it be any size? would it be practical | - Is it necessary to have the page size be a power of 2? Could it be any size? would it be practical | ||
| + | - Consider an array of size 1000-by-1000 double words. A direct mapped 64KB with a block size of 128 bytes. How many miss if we accessed the cache in a row-major fashion? A column major fashion? Assume that the array is stored in a row major fashion | ||
| - Consider a toy cache with 8-byte block size and capacity of 64 bytes. which of these references are hits and which are miss | - Consider a toy cache with 8-byte block size and capacity of 64 bytes. which of these references are hits and which are miss | ||
assignments/a2.txt · Last modified: 2018/10/11 18:40 by aboelaze