Differences

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--- labs [2019/02/26 19:57] – nsajadi
+++ labs [2019/03/23 03:28] (current) – nsajadi
@@ Line 13: / Line 13: @@
 Where <directory> is the name of the folder contains all prelab files. For more information about the submit command in labs, please check [[https://wiki.eecs.yorku.ca/dept/tdb/services:submit:cli-submit|here]] and for submitting from outside labs please check [[https://wiki.eecs.yorku.ca/dept/tdb/login:start|here]].
+When you submit your files as prelabs activities, make sure they are ASCII files, i.e., only contains printable characters, otherwise they wont be appeared during the lab test session. To make sure your file contains only printable characters use "file" command in the Linux environment. If the file command reports the file is ASCII file your file be accessible during the lab test otherwise you don't have access to them.
 Note that the due date for submitting prelabs is 10 minutes before the lab test starts.
@@ Line 58: / Line 60: @@
 ====== Prelabs ======
-**Acknowledgement**: The following tutorials are developed by professor Hamzeh Roumani for MIPS ISA. Lab B-D are modified by Dr. Nick Sajadi to adopt RISK-V ISA.
+**Acknowledgement**: The following tutorials are developed by professor Hamzeh Roumani for MIPS ISA. Lab B-D and M-N are modified by Dr. Nick Sajadi to adopt RISK-V ISA.
+RISK-V ISA:
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labA.pdf| labA]]
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labB-RISK-V.pdf| labB]]
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labC-RISK-V.pdf| labC]]
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labD-RISK-V.pdf| labD]]
+RISK-V Single Cycle Data path:
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labK.pdf| labK]]
+    * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labL.pdf| labL]]
+    * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labM-RISK-V.pdf| labM]], [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/LabM-N-RISK-V-Verilog-Modules.zip| Here ]] are verilog required modules if you use installed verilog in your machine. Use these modules after the name of your module when you compile your code.[[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/testCPU.v|Here]] you can find the ultimate cpu tester.
+    * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labN-RISK-V.pdf| labN]]