Differences

This shows you the differences between two versions of the page.

--- labs [2019/03/12 19:57] – nsajadi
+++ labs [2019/03/23 03:28] (current) – nsajadi
@@ Line 60: / Line 60: @@
 ====== Prelabs ======
-**Acknowledgement**: The following tutorials are developed by professor Hamzeh Roumani for MIPS ISA. Lab B-D are modified by Dr. Nick Sajadi to adopt RISK-V ISA.
+**Acknowledgement**: The following tutorials are developed by professor Hamzeh Roumani for MIPS ISA. Lab B-D and M-N are modified by Dr. Nick Sajadi to adopt RISK-V ISA.
+RISK-V ISA:
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labA.pdf| labA]]
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labB-RISK-V.pdf| labB]]
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labC-RISK-V.pdf| labC]]
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labD-RISK-V.pdf| labD]]
+RISK-V Single Cycle Data path:
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labK.pdf| labK]]
     * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labL.pdf| labL]]
+    * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labM-RISK-V.pdf| labM]], [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/LabM-N-RISK-V-Verilog-Modules.zip| Here ]] are verilog required modules if you use installed verilog in your machine. Use these modules after the name of your module when you compile your code.[[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/testCPU.v|Here]] you can find the ultimate cpu tester.
+    * [[https://www.eecs.yorku.ca/~nsajadi/Teaching/EECS2021/Labs/labN-RISK-V.pdf| labN]]