====== LABS ======

===== Lab 0 =====

Check the eclass

===== LAB 1 =====

{{:lab_1.pdf|}}


===== LAB 2 =====

{{:lab_2-desktop-btqj33p-desktop-btqj33p.pdf|LAB 2}}





===== LAB 3 =====

{{:lab_3.pdf|LAB 3}}

The Verilog code should be according to the following prototype. It will be submitted separately using //**submit**// or //**websubmit**//

//**module**// trafficlight (

//**input**// rst, / / resets the system to the initial state (main road green

//**input**// request, / / car sensor ored with pedestrian request

//**input**// clk, / / system clock

//**output**// reg [5:0] light, / / MainG MainY MainR SecG SecY SecR

//**output**// reg [7:0] sevseg / / dot g  f  e   d   c   b   a

);

//**endmodule**//

-----------------------



===== LAB 4 =====

{{:lab_4.pdf|LAB 4}}



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===== LAB 5 =====

Her is {{:lab_5_1.pdf|LAB 5}} due March 21


===== LAB 6 =====

{{:lab_6_2020.pdf|LAB 6}}