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--- course_outline [2021/01/15 18:01] – aboelaze
+++ course_outline [2021/01/21 21:04] (current) – aboelaze
@@ Line 26: / Line 26: @@
 === By the end of the course, students should be able to ===
-  * Model systems using the appropriate modelling technique
+  * Model different systems using the appropriate modelling technique
-  *
+  * Design and implement digital systems from specifications
+  * Test and validate the proposed digital system
+===== Tentative Schedule =====
+  * week 1: Introduction to Embedded and cyber-physical systems
+  * Week 2: Modeling continuous and discrete systems
+  * Week 3: Implementation issues and Introduction to SystemVerilog
+  * Week 4: Continue with the above and Composition of state machines
+  * Week 5: ASM and implementation in SystemVerilog
+  * Week 6: Concurrent Models of Computations
+  * Week 7: Sensors and actuators
+  * Week 8: Equivalence and refinement
+  * Week 9: Model checking and reachability analysis
+  * Week 10: Testbenches and verification
+  * Week 11: Complex digital systems
+  * Week 12: