Table of Contents

IC Compiler Script Notes

Synopsys Home

Synopsys provides a bunch of Tcl scripts as part of their reference methodology (rm) offering. An incomplete view into this flow for the ICC tool is shown below.

0.1 init_design_icc.tcl (rm_icc_scripts)

This script reads the logic design netlist and constraints, creates the floorplan or reads the floorplan from a DEF or floorplan file, and generates a zero interconnect timing report. The purpose of this script is to hand off a floorplanned design to the place_opt step, which is the next step in the flow. Depending on the input format (Milkyway, Verilog, or .ddc), the script reads the appropriate files and includes the floorplan information that already exists in the initial floorplanned design or that is provided in a separate DEF file. For a Milkyway CEL view or a .ddc file, no SDC constraints are loaded because the constraints are assumed to exist in the CEL view or .ddc file. For a Verilog netlist file, the read_sdc command is also executed. If you need to add floorplan constraints such as placement or routing blockages or different multivoltage or multicorner-multimode features, it is recommended that you do this in the file after reading in the design. Comments and commands in the scripts advise you where to specify the floorplan inputs. The name of the output design saved in this step is: init_design_icc.

0.2 flat_dp.tcl (rm_icc_dp_scripts)

This file runs a flat design planning flow to show routability, timing, and IR drop of the design.

The floorplan describes the size of the core; the shape and placement of standard cell rows and routing channels; standard cell placement constraints; and the placement of peripheral I/O, power, ground, corner, and filler pad cells.

There are two modes controlled by the ICC_DP_EXPLORE_MODE variable in the icc_setup.tcl file.

Baseline mode, which sources baseline.tcl, serves as a reference and template. All the steps are in the script. It includes detailed comments to describe usage of commands. You have the freedom to further customize the steps based on your design style.

Explore mode, which sources macro_placement_exploration_dp.tcl, is capable of performing the same flow multiple times automatically, each time with different combinations of settings. It ends by summarizing the results of each run in an HTML table that contains links to logs, reports, and a snapshot of each run. Explore mode runs the same flow as baseline mode. However, it uses a procedure to run multiple times automatically.

0.3 place_opt_icc.tcl (rm_icc_scripts)

This script executes the placement and placement-based optimization steps. After reading the initial design created by init_design_icc.tcl, the script sources two files, rm_icc_scripts/common_placement_settings_icc.tcl and rm_icc_scripts/common_optimization_settings_icc.tcl. These files contain several recommended settings for use during each of the succeeding optimization steps. The name of the output design saved in this step is place_opt_icc.

0.4 clock_opt_cts_icc.tcl (rm_icc_scripts)

The purpose of this script is to execute the clock tree synthesis and clock tree optimization steps: The script sources rm_icc_scripts/common_cts_settings_icc.tcl, which you must edit when you need to define any clock tree specific requirements, such as nondefault routing rules, layers, constraints, or shielding. See rm_icc_scripts/common_cts_settings_icc.tcl for more examples in creating NDR and shielding rules. To enable interclock delay balancing, use the ICC_INTERCLOCK_BALANCING* variables in rm_setup/icc_setup.tcl. These variables enable interclock delay balancing during clock tree synthesis. To enable the update clock latency capability, use the ICC_CTS_UPDATE_LATENCY and ICC_CTS_LATENCY_OPTIONS_FILE variables in rm_setup/icc_setup.tcl. These variables enable clock latency updates during clock tree synthesis. To enable the self-gating logic insertion capability, set the ICC_CTS_SELF_GATING_SAIF_FILE variable in rm_setup/icc_setup.tcl. This variable enables self-gating logic insertion during clock tree synthesis. The name of the output design saved in this step is clock_opt_cts_icc.

0.5 clock_opt_psyn_icc.tcl (rm_icc_scripts)

0.6 clock_opt_route_icc.tcl (rm_icc_scrips)

0.7 route_icc.tcl (rm_icc_scripts)

0.8 route_opt_icc.tcl (rm_icc_scripts)

0.9 chip_finish_icc.tcl (rm_icc_scripts)

0.10 signoff_opt_icc

0.11 metal_fill_icc

0.12 outputs_icc.tcl (rm_icc_scripts)

0.13 ic

  1. initialize_floorplan (create_floorplan): In /rm_icc_scripts/init_design_icc.tcl Here you can set how close the design comes to your i/o pins.
  2. create_rectilinear_rings (in Preroute → Create Rings…)