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--- icc-par:ic_compiler_script_notes [2014/05/03 23:35] – magiero
+++ icc-par:ic_compiler_script_notes [2014/05/03 23:56] (current) – magiero
@@ Line 11: / Line 11: @@
 For a Milkyway CEL view or a .ddc file, no SDC constraints are loaded because the constraints are assumed to exist in the CEL view or .ddc file. For a Verilog netlist file, the ''read_sdc'' command is also executed.
 If you need to add floorplan constraints such as placement or routing blockages or different multivoltage or multicorner-multimode features, it is recommended that you do this in the file after reading in the design. Comments and commands in the scripts advise you where to specify the floorplan inputs.
-The name of the output design saved in this step is: init_design_icc.
+The name of the output design saved in this step is: ''init_design_icc''.
   * ''icc_setup.tcl'' (//in rm_setup//): Whole bunch of ICC variables set.
@@ Line 27: / Line 27: @@
 ==== - flat_dp.tcl (rm_icc_dp_scripts) ====
+This file runs a flat design planning flow to show routability, timing, and IR drop of the design.
 The floorplan describes the size of the core; the shape and placement of standard cell rows and routing channels; standard cell placement constraints; and the placement of peripheral I/O, power, ground, corner, and filler pad cells.
+There are two modes controlled by the ICC_DP_EXPLORE_MODE variable in the icc_setup.tcl file.
+Baseline mode, which sources ''baseline.tcl'', serves as a reference and template. All the steps are in the script. It includes detailed comments to describe usage of commands. You have the freedom to further customize the steps based on your design style.
+Explore mode, which sources ''macro_placement_exploration_dp.tcl'', is capable of performing the same flow multiple times automatically, each time with different combinations of settings. It ends by summarizing the results of each run in an HTML table that contains links to logs, reports, and a snapshot of each run.  Explore mode runs the same flow as baseline mode. However, it uses a procedure to run multiple times automatically.
   * ''icc_setup.tcl'' (//in rm_setup//): Called at the beginning of all scripts.
@@ Line 80: / Line 88: @@
 ==== - place_opt_icc.tcl (rm_icc_scripts) ====
+This script executes the placement and placement-based optimization steps. After reading the initial design created by ''init_design_icc.tcl'', the script sources two files, ''rm_icc_scripts/common_placement_settings_icc.tcl'' and ''rm_icc_scripts/common_optimization_settings_icc.tcl''. These files contain several recommended settings for use during each of the succeeding optimization steps.  The name of the output design saved in this step is ''place_opt_icc''.
   * ''icc_setup.tcl'' (//in rm_setup//): Called at the beginning of all scripts.\\
   * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
@@ Line 92: / Line 103: @@
 ==== - clock_opt_cts_icc.tcl (rm_icc_scripts) ====
+The purpose of this script is to execute the clock tree synthesis and clock tree
+optimization steps:
+The script sources ''rm_icc_scripts/common_cts_settings_icc.tcl'', which you must edit when you need to define any clock tree specific requirements, such as nondefault routing rules, layers, constraints, or shielding.
+See ''rm_icc_scripts/common_cts_settings_icc.tcl'' for more examples in creating NDR and shielding rules.
+To enable interclock delay balancing, use the ICC_INTERCLOCK_BALANCING* variables in ''rm_setup/icc_setup.tcl''. These variables enable interclock delay balancing during clock tree synthesis.
+To enable the update clock latency capability, use the ICC_CTS_UPDATE_LATENCY and ICC_CTS_LATENCY_OPTIONS_FILE variables in ''rm_setup/icc_setup.tcl''. These variables enable clock latency updates during clock tree synthesis.
+To enable the self-gating logic insertion capability, set the ICC_CTS_SELF_GATING_SAIF_FILE variable in ''rm_setup/icc_setup.tcl''. This variable enables self-gating logic insertion during clock tree synthesis.
+The name of the output design saved in this step is ''clock_opt_cts_icc''.
   * ''icc_setup.tcl'' (//in rm_setup//)\\
   * __''open_mw_lib''__\\
@@ Line 101: / Line 122: @@
   * __''set_app_var''__\\
   * __''set_delay_calculation''__\\
-  * __**''clock_opt'' -only_cts -no_clock_route**__: Perform clock tree synthesis.\\
+  * __**''clock_opt -only_cts -no_clock_route''**__: Perform clock tree synthesis.\\
   * __''derive_pg_connection''__\\
   * ''common_post_cts_timing_settings.tcl'' (//in rm_icc_scripts//)\\