Electronic Machine Intelligence Lab (EMIL)

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====== IC Compiler Script Notes ======

[[syndocs: | Synopsys Home]]

Synopsys provides a bunch of Tcl scripts as part of their **reference methodology** (rm) offering.  An incomplete view into this flow for the ICC tool is shown below.

==== - init_design_icc.tcl (rm_icc_scripts) ====

This script reads the logic design netlist and constraints, creates the floorplan or reads the floorplan from a DEF or floorplan file, and generates a zero interconnect timing report.
The purpose of this script is to hand off a floorplanned design to the ''place_opt'' step, which is the next step in the flow. Depending on the input format (Milkyway, Verilog, or .ddc), the script reads the appropriate files and includes the floorplan information that already exists in the initial floorplanned design or that is provided in a separate DEF file.
For a Milkyway CEL view or a .ddc file, no SDC constraints are loaded because the constraints are assumed to exist in the CEL view or .ddc file. For a Verilog netlist file, the ''read_sdc'' command is also executed.
If you need to add floorplan constraints such as placement or routing blockages or different multivoltage or multicorner-multimode features, it is recommended that you do this in the file after reading in the design. Comments and commands in the scripts advise you where to specify the floorplan inputs.
The name of the output design saved in this step is: ''init_design_icc''.

  * ''icc_setup.tcl'' (//in rm_setup//): Whole bunch of ICC variables set.
    * ''make_generated_vars.tcl'': Generated in the ''Makefile'' and defines some basic stuff.
    * ''common_setup.tcl'' (//in rm_setup//): Basic definitions like VDD and VSS.
    * __''set_mw_lib_reference $MW_DESIGN_LIBRARY -mw_reference_library *''__
    * ''check_icc_rm_values.tcl'' (//in rm_icc_scripts//): Exits ICC if script error.\\
  * __''open_mw_cel''__\\
  * __**''initialize_floorplan''**__: Make an initial floorplan.\\
  * __''$ICC_PHYSICAL_CONSTRAINTS_FILE''__ (optional)\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//)\\
  * ''common_placement_settings_icc.tcl'' (// in rm_icc_scripts//)\\
  * __''derive_pg_connection''__\\
  * __''save_mw_cell''__

==== - flat_dp.tcl (rm_icc_dp_scripts) ====

This file runs a flat design planning flow to show routability, timing, and IR drop of the design.

The floorplan describes the size of the core; the shape and placement of standard cell rows and routing channels; standard cell placement constraints; and the placement of peripheral I/O, power, ground, corner, and filler pad cells.

There are two modes controlled by the ICC_DP_EXPLORE_MODE variable in the icc_setup.tcl file.

Baseline mode, which sources ''baseline.tcl'', serves as a reference and template. All the steps are in the script. It includes detailed comments to describe usage of commands. You have the freedom to further customize the steps based on your design style.

Explore mode, which sources ''macro_placement_exploration_dp.tcl'', is capable of performing the same flow multiple times automatically, each time with different combinations of settings. It ends by summarizing the results of each run in an HTML table that contains links to logs, reports, and a snapshot of each run.  Explore mode runs the same flow as baseline mode. However, it uses a procedure to run multiple times automatically.

  * ''icc_setup.tcl'' (//in rm_setup//): Called at the beginning of all scripts.
  * ''proc_explore.tcl'' (//in rm_icc_dp_scripts//)
    * __''dp_explore''__
    * __''set_host_options''__
    * __''set_fp_placement_strategy''__
    * __''create_fp_placement''__: 
    * __''synthesize_fp_rail''__
    * __''commit_fp_rail''__
    * __''create_fp_virtual_pad''__ (optional)
    * __''analyze_fp_rail''__
    * __''optimize_fp_timing''__
    * __''route_zrt_global''__ OR __''route_global''__
    * __''remove_route_by_type''__
    * __''extract_rc''__
    * __''create_qor_snapshot''__
    * __''report_timing''__
    * __''report_qor_snapshot''__
    * __''write_floorplan''__
    * __''write_pin_pad_physical_constraints''__
    * __''write_def''__
  * __''gui_set_current_task''__
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ONE OF: ''macro_placement_exploration_dp.tcl'' OR ''baseline.tcl'' (//both in rm_icc_dp_scripts//), for baseline...
    * __**''create_fp_placement''**__: Place the standard cells in your boundary.
    * __''route_fp_proto''__
    * __''save_mw_cell''__
    * __''remove_route_by_type''__
    * __''extract_rc''__
    * __''create_qor_snapshot''__
    * __**''synthesize_fp_rail''**__: Synthesize the power rails.  Can see estimated rail voltage drops.
    * __''commit_fp_rail''__: Commit power plan if power budget is met.
    * __**''analyze_fp_rail''**__
    * ''common_optimization_settings_icc.tcl''
    * __''extract_rc''__
    * __''report_timing''__
    * __''optimize_fp_timing''__
    * __''route_fp_proto''__
    * __''save_mw_cel''__
    * __''remove_route_by_type''__
    * __''extract_rc''__
    * __''create_qor_snapshot''__
    * __''report_qor_snapshot''__
    * __''report_timing''__
    * __''set_dont_touch_placement''__
    * __''save_mw_cel''__
    * __''write_floorplan''__
    * __''write_pin_pad_physical_constraints''__

==== - place_opt_icc.tcl (rm_icc_scripts) ====

This script executes the placement and placement-based optimization steps. After reading the initial design created by ''init_design_icc.tcl'', the script sources two files, ''rm_icc_scripts/common_placement_settings_icc.tcl'' and ''rm_icc_scripts/common_optimization_settings_icc.tcl''. These files contain several recommended settings for use during each of the succeeding optimization steps.  The name of the output design saved in this step is ''place_opt_icc''.

  * ''icc_setup.tcl'' (//in rm_setup//): Called at the beginning of all scripts.\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_cts_settings.tcl'' (//in rm_icc_scripts//): Clock tree synthesis.  Set in place_opt and clock_opt sessions.\\
  * __''open_mw_lib''__\\
  * __''copy_mw_cel''__\\
  * __''open_mw_cel''__\\
  * __**''place_opt''**__\\
  * __''derive_pg_connection''__\\
  * __''save_mw_cell''__

==== - clock_opt_cts_icc.tcl (rm_icc_scripts) ====

The purpose of this script is to execute the clock tree synthesis and clock tree
optimization steps:
The script sources ''rm_icc_scripts/common_cts_settings_icc.tcl'', which you must edit when you need to define any clock tree specific requirements, such as nondefault routing rules, layers, constraints, or shielding.
See ''rm_icc_scripts/common_cts_settings_icc.tcl'' for more examples in creating NDR and shielding rules.
To enable interclock delay balancing, use the ICC_INTERCLOCK_BALANCING* variables in ''rm_setup/icc_setup.tcl''. These variables enable interclock delay balancing during clock tree synthesis.
To enable the update clock latency capability, use the ICC_CTS_UPDATE_LATENCY and ICC_CTS_LATENCY_OPTIONS_FILE variables in ''rm_setup/icc_setup.tcl''. These variables enable clock latency updates during clock tree synthesis.
To enable the self-gating logic insertion capability, set the ICC_CTS_SELF_GATING_SAIF_FILE variable in ''rm_setup/icc_setup.tcl''. This variable enables self-gating logic insertion during clock tree synthesis.
The name of the output design saved in this step is ''clock_opt_cts_icc''.

  * ''icc_setup.tcl'' (//in rm_setup//)\\
  * __''open_mw_lib''__\\
  * __''copy_mw_cel''__\\
  * __''open_mw_cel''__\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_cts_settings.tcl'' (//in rm_icc_scripts//): Clock tree synthesis.  Set in place_opt and clock_opt sessions.\\
  * __''set_app_var''__\\
  * __''set_delay_calculation''__\\
  * __**''clock_opt -only_cts -no_clock_route''**__: Perform clock tree synthesis.\\
  * __''derive_pg_connection''__\\
  * ''common_post_cts_timing_settings.tcl'' (//in rm_icc_scripts//)\\
  * __''remove_ideal_network''__\\
  * __''set_fix_hold''__\\
  * __''save_mw_cel''__

==== - clock_opt_psyn_icc.tcl (rm_icc_scripts) ====
  * ''icc_setup.tcl''\\
  * __''open_mw_lib''__\\
  * __''copy_mw_cel''__\\
  * __''open_mw_cel''__\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_cts_settings.tcl'' (//in rm_icc_scripts//): Clock tree synthesis.  Set in place_opt and clock_opt sessions.\\
  * ''common_post_cts_timing_settings_icc.tcl (//in rm_icc_scripts//)''\\
  * __''set_app_var''__\\
  * __''extract_rc''__\\
  * __**''clock_opt -no_clock_route -only_psyn -area_recovery''**__\\
  * __''route_group''__\\
  * __''derive_pg_connection''__\\
  * __''same_mw_cel''__

==== - clock_opt_route_icc.tcl (rm_icc_scrips) ====
  * ''icc_setup.tcl'' (//in rm_setup//)\\
  * __''open_mw_lib''__\\
  * __''copy_mw_cel''__\\
  * __''open_mw_cel''__\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_cts_settings.tcl'' (//in rm_icc_scripts//): Clock tree synthesis.  Set in place_opt and clock_opt sessions.\\
  * ''common_post_cts_timing_settings.tcl''\\
  * ''common_route_si_settings_icc.tcl'' (//in rm_icc_scripts//)\\
  * __''set_si_options''__: Turn off SI for clock routing\\
  * __''set_delay_calculation''__\\
  * __''set_route_mode_options''__\\
  * __''optimize_clock_tree''__\\
  * __''derive_pg_connection''__\\
  * __''save_mw_cel''__

==== - route_icc.tcl (rm_icc_scripts) ====
  * ''icc_setup.tcl'' (//in rm_setup//)\\
  * __''open_mw_lib''__\\
  * __''copy_mw_cel''__\\
  * __''open_mw_cel''__\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_cts_settings.tcl'' (//in rm_icc_scripts//): Clock tree synthesis.  Set in place_opt and clock_opt sessions.\\
  * ''common_post_cts_timing_settings.tcl''\\
  * ''common_route_si_settings_icc.tcl'' (//in rm_icc_scripts//)\\
  * __''set_route_mode_options''__: Load route and SI settings.
  * __''report_preferred_routing_direction''__: Check routability.
  * __''report_tlu_plus_files''__
  * __**''route_opt -initial_route_only -num cpus *''**__: Initial route. CPU count can be set to 1 as a minimum.
  * __''update_clock_latency''__


==== - route_opt_icc.tcl (rm_icc_scripts) ====
  * ''icc_setup.tcl'' (//in rm_setup//)\\
  * __''open_mw_lib''__\\
  * __''copy_mw_cel''__\\
  * __''open_mw_cel''__\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_post_cts_timing_settings.tcl'' (//in rm_icc_scripts//) \\
  * ''common_route_si_settings_icc.tcl'' (//in rm_icc_scripts//)\\
  * __''set_app_var compile_instance_name_prefix icc_route_opt''__: Start post route optimization.\\
  * __''set_route_mode_options -zroute false''__\\
  * __**''route_opt -skip_initial_route -effort * -xtalk_reduction''**__: ''effort'' can be set to "low"\\
  * __''derive_pg_connection''__\\
  * __''save_mw_cel''__

==== - chip_finish_icc.tcl (rm_icc_scripts) ====
  * ''icc_setup.tcl'' (//in rm_setup//)\\
  * __''open_mw_lib''__\\
  * __''copy_mw_cel''__\\
  * __''open_mw_cel''__\\
  * ''common_optimization_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_placement_settings_icc.tcl'' (//in rm_icc_scripts//): In all scripts.\\
  * ''common_post_cts_timing_settings.tcl'' (//in rm_icc_scripts//) \\
  * ''common_route_si_settings_icc.tcl'' (//in rm_icc_scripts//): Loads the route and SI settings.\\
  * __''set_droute_options -name doAntennaConx -value 4''__: Antenna fixing.\\
  * __''report_antenna_rules''__: Antenna fixing\\
  * __''route_search_repair -rerun_drc -loop 10''__: Antenna fixing.\\
  * __''report_antenna_ratio''__: Antenna fixing\\
  * __''insert_diode -no_auto_cell_selection -diode_cells *''__: Antenna fixing.\\
  * __''route_search_repair -rerun_drc -loop 3''__: Antenna fixing.\\
  * __''report_antenna_ration''__: Antenna fixing.\\
  * __''route_spreadwires''__: Wire spreading for shorts.\\
  * __''route_widen_wire''__: Wire widening for opens.\\
  * __''set_app_var droute_optViaTimingDriven 1''__: Timing driven redundant via insertion.\\
  * __''interst_redundant_vias -auto_mode insert -num_cpus *''__\\
  * __**''insert_stdcell_filler -cell_without_metal $FILLER_CELL -connect_to_power "VDD" -connect_to_ground "VSS"''**__: $FILLER_CELL defined in make_generated_vars.tcl.\\
  * __**''route_opt -incremental -size_only''**__: Incremental timing optimization.\\
  * __''route_search_repair -rerun_drc -num_cpus 1 -loop 2''__\\
  * __''derive_pg_connection''__\\
  * __''save_mw_cel''__
  


==== - signoff_opt_icc ====
==== - metal_fill_icc ====
==== - outputs_icc.tcl (rm_icc_scripts) ====
  * ''icc_setup.tcl'' (//in rm_setup//)\\
  * __''open_mw_cel metal_fill_icc -lib *_LIB''__\\
  * __**''change_names -rules verilog -hierarchy''**__\\
  * __''save_mw_cel -as change_names_icc''__\\
  * __''close_mw_cel''__\\
  * __''open_mw_cel change_names_icc''__\\
  * __**''write_verilog -diode_ports -no_physical_only_cells *.output.v''**__\\
  * __**''write_verilog -no_physical_only_cells *.output.dc.v''**__\\
  * __**''write_verilog -diode_ports -pg *.output.pg.lvs.v''**__\\
  * __''set_app_var write_sdc_output_lumped_net_capacitance false''__\\
  * __''set_app_var write_sdc_output_net_resistance false''__\\
  * __**''write_sdc *.output.sdc''**__\\
  * __**''extract_rc -coupling_cap''**__\\
  * __**''write_parasitics  -format SBPF -output *.output.sbpf''**__\\
  * __''write_def -output *.output.def''__\\
  * __''save_mw_cel''__\\
  * __''close_mw_cel''__\\
  * __''open_mw_cel''__\\
  * __''create_ilm -include_xtalk''__\\
  * __''create_macro_fram''__\\
  * __''set_droute_options -name doAntennaConx -value 4''__\\
  * __''extract_hier_antenna_property -cell_name *''__\\
  * __''close_mw_cel''__



==== - ic ====

  - ''initialize_floorplan'' (''create_floorplan''): In ''/rm_icc_scripts/init_design_icc.tcl''  Here you can set how close the design comes to your i/o pins.\\
  - ''create_rectilinear_rings'' (in Preroute -> Create Rings...)