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--- brg334_-_electronics_teaching_lab:start [2026/08/20 21:34] – mdaminul
+++ brg334_-_electronics_teaching_lab:start [2026/08/20 22:14] (current) – mdaminul
@@ Line 71: / Line 71: @@
+==== EECS 4612: Digital VLSI ====
+  * [[https://wiki.eecs.yorku.ca/lab/teaching/_media/brg334_-_electronics_teaching_lab:4612_lab1_cadence_tutorial.pdf|LAB1: Introduction to Simulation in Cadence]]
+  * [[https://wiki.eecs.yorku.ca/lab/teaching/_media/brg334_-_electronics_teaching_lab:4612_lab2_layout_extraction_tutorial.pdf|LAB2: Tutorial on Layout Extraction]]
+  * [[https://wiki.eecs.yorku.ca/lab/teaching/_media/brg334_-_electronics_teaching_lab:4612_project_1_-_schematic_and_layout_design_of_a_2-input_nand_gate.pdf|PROJECT1: Schematic and Layout Design of a 2-input NAND Gate]]
+  * [[https://wiki.eecs.yorku.ca/lab/teaching/_media/brg334_-_electronics_teaching_lab:4612_project_2_post-layout_simulation_of_a_complex_logic_gate.pdf|PROJECT2: Post-Layout simulation of a Complex Logic Gate]]
+  * [[https://wiki.eecs.yorku.ca/lab/teaching/_media/brg334_-_electronics_teaching_lab:4612_project_3_rtl-to-gds_design_flow.pdf|PROJECT3: RTL-to-GDS ASIC Design Flow Tutorial]]
+  * [[https://wiki.eecs.yorku.ca/lab/teaching/_media/brg334_-_electronics_teaching_lab:4612_term_project_design_of_a_32-bit_alu.pdf|TERM PROJECT: Design of a 32-Bit ALU]]