verilog_modules
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Table of Contents
Verilog Modules
So far we have been writing Verilog top-level modules that test components. In this lecture we learn how to write te components themselves.
Outline
- Performing PC+4 using the main ALU
- Performing PC+4 + 4*Label using the main ALU
- Adding registers to hold intermediate data
- Combining the two memory units
- Issuing the control signals for State #0
- Doing something useful in State #1
- Instruction-dependent states
To Do
- Unordered List Item
- Unordered List Item
- Look at the program
alu1band its testeralu1bClientin the Resource Directory.alu1b' is a 1-bit adder component made up of basic gates. * Look at the programalu2band its testeralu2bClientin the Resource Directory.alu2b' is a 2-bit adder component made up of twoalu1badders.
verilog_modules.1195175892.txt.gz · Last modified: 2007/11/16 01:18 by roumani